Unit 4: Central Processing Unit

Opening Hook — Apple M4 vs Snapdragon X Elite: The CPU War

Learning Outcomes — Bloom's Taxonomy Mapped

Concept Explanation — CPU Architecture from Scratch

1. General Register Organization

A CPU's register organization determines how data flows between registers, the ALU, and memory. In a general register organization, the CPU has a set of general-purpose registers (typically R0–R7), and any register can be used as a source or destination for any operation. This is the most flexible and common organization used in modern CPUs.

ASCII DIAGRAM
     ┌──────────────────────────────────────────┐
     │          REGISTER FILE (R0 – R7)         │
     │  ┌────┬────┬────┬────┬────┬────┬────┬────┐│
     │  │ R0 │ R1 │ R2 │ R3 │ R4 │ R5 │ R6 │ R7 ││
     │  └────┴────┴────┴────┴────┴────┴────┴────┘│
     └─────────┬──────────────────┬──────────────┘
               │                  │
          ┌────▼─────┐      ┌────▼─────┐
          │  MUX  A  │      │  MUX  B  │
          │ (SELA)   │      │ (SELB)   │
          └────┬─────┘      └────┬─────┘
               │   Input A       │  Input B
               ▼                 ▼
          ┌──────────────────────────┐
          │      A   L   U          │
          │     (OPR — 5 bits)      │
          └────────────┬────────────┘
                       │
                  Output Bus
                       │
                  ┌────▼─────┐
                  │  SELD    │ ← Destination register select
                  │ (3 bits) │
                  └──────────┘
                       │
               (writes back to Register File)

Control Word Format (14 bits)

Example: R3 ← R1 + R2

Complete control word: 001 010 011 00010 (14 bits)

2. Stack Organization

A stack is a last-in-first-out (LIFO) storage structure. In CPU architecture, stacks are used for subroutine calls (saving return addresses), expression evaluation, and interrupt handling. The stack is managed by a special register called the Stack Pointer (SP).

MEMORY STACK
    Address    Memory        Notes
    ┌────────┬────────────┐
    │  4000  │  (empty)   │  ← Initial SP (stack empty)
    ├────────┼────────────┤
    │  3999  │  Data_3    │  ← SP after 3 PUSHes (Top of Stack)
    ├────────┼────────────┤
    │  3998  │  Data_2    │
    ├────────┼────────────┤
    │  3997  │  Data_1    │  ← First item pushed
    ├────────┼────────────┤
    │  ...   │   ...      │
    ├────────┼────────────┤
    │  3000  │  (limit)   │  ← Stack bottom (overflow if SP < 3000)
    └────────┴────────────┘

    Stack grows DOWNWARD (address decreases on PUSH)
    Stack shrinks UPWARD (address increases on POP)
    FULL condition:  SP = 3000 (stack bottom limit)
    EMPTY condition: SP = 4000 (initial value)

0-Address Instructions & Stack-Based Expression Evaluation

In 0-address (stack) architecture, instructions like ADD don't specify operands — they implicitly pop two values from the stack, operate, and push the result. This is how the expression (A+B)×C is evaluated using Reverse Polish Notation (RPN).

Infix: (A + B) × C     RPN (Postfix): A B + C ×

Assume A=3, B=5, C=4:

3. Instruction Formats

An instruction format defines the layout of bits in a machine instruction — how many addresses (operands) are specified, what fields are present, and how long each field is. The number of address fields determines the instruction type.

Evaluating X = (A + B) × (C + D) in All Four Formats

3-Address Format: OP DEST, SRC1, SRC2

3-ADDRESS
Instruction 1:  ADD  R1, A, B      ; R1 ← M[A] + M[B]
Instruction 2:  ADD  R2, C, D      ; R2 ← M[C] + M[D]
Instruction 3:  MUL  X,  R1, R2    ; M[X] ← R1 × R2

Total instructions: 3
Advantage: Fewest instructions, most information per instruction
Disadvantage: Longest instruction word (3 address fields)

2-Address Format: OP DEST, SRC (DEST ← DEST op SRC)

2-ADDRESS
Instruction 1:  MOV  R1, A      ; R1 ← M[A]
Instruction 2:  ADD  R1, B      ; R1 ← R1 + M[B]        → R1 = A+B
Instruction 3:  MOV  R2, C      ; R2 ← M[C]
Instruction 4:  ADD  R2, D      ; R2 ← R2 + M[D]        → R2 = C+D
Instruction 5:  MUL  R1, R2     ; R1 ← R1 × R2          → R1 = (A+B)×(C+D)
Instruction 6:  MOV  X,  R1     ; M[X] ← R1

Total instructions: 6
Advantage: Moderate instruction length
Disadvantage: One source is always overwritten (destructive)

1-Address Format: OP ADDR (uses Accumulator AC implicitly)

1-ADDRESS
Instruction 1:  LOAD  A        ; AC ← M[A]
Instruction 2:  ADD   B        ; AC ← AC + M[B]        → AC = A+B
Instruction 3:  STORE T        ; M[T] ← AC             → save A+B
Instruction 4:  LOAD  C        ; AC ← M[C]
Instruction 5:  ADD   D        ; AC ← AC + M[D]        → AC = C+D
Instruction 6:  MUL   T        ; AC ← AC × M[T]        → AC = (C+D)×(A+B)
Instruction 7:  STORE X        ; M[X] ← AC

Total instructions: 7
Advantage: Short instruction word
Disadvantage: Needs temporary storage, more instructions

0-Address Format: OP (uses Stack implicitly)

0-ADDRESS
Instruction 1:  PUSH  A        ; TOS ← A
Instruction 2:  PUSH  B        ; TOS ← B
Instruction 3:  ADD             ; Pop B,A; Push A+B
Instruction 4:  PUSH  C        ; TOS ← C
Instruction 5:  PUSH  D        ; TOS ← D
Instruction 6:  ADD             ; Pop D,C; Push C+D
Instruction 7:  MUL             ; Pop (C+D),(A+B); Push (A+B)×(C+D)
Instruction 8:  POP   X        ; M[X] ← TOS

Total instructions: 8
Advantage: Shortest instruction word, hardware-friendly
Disadvantage: Most instructions needed, stack management overhead

Comparison of Instruction Formats

4. Addressing Modes — All 8

An addressing mode specifies how the CPU calculates the effective address (EA) of an operand. Different modes provide different trade-offs between flexibility, speed, and code compactness. Mastering all 8 modes is essential for GATE and CPU design.

Mode 1: Immediate Addressing

Definition: The operand value is directly contained in the instruction itself. No memory access needed for operand.

EA: No effective address — operand is part of instruction.

IMMEDIATE
  Instruction: [ OP | #25 ]
                      │
                      └── Operand = 25 (directly in instruction)

  Example: MOV R1, #25    → R1 = 25
  Use: Loading constants, initializing counters
  Speed: ★★★★★ Fastest (no memory access for operand)

Mode 2: Direct Addressing

Definition: The address field contains the actual memory address of the operand.

EA = Address field of instruction

DIRECT
  Instruction: [ OP | 500 ]
                      │
                      ▼
               Memory[500] = 42   ← Operand

  EA = 500, Operand = 42
  Example: LOAD 500        → AC = M[500] = 42
  Use: Accessing global variables
  Speed: ★★★★ One memory access

Mode 3: Indirect Addressing

Definition: The address field points to a memory location that contains the effective address. Two memory accesses needed.

EA = M[Address field]

INDIRECT
  Instruction: [ OP | 500 ]
                      │
                      ▼
               Memory[500] = 800   ← This is the EA (pointer)
                      │
                      ▼
               Memory[800] = 42    ← Actual operand

  EA = 800, Operand = 42
  Example: LOAD @500       → AC = M[M[500]] = M[800] = 42
  Use: Pointers, dynamic memory access, linked lists
  Speed: ★★★ Two memory accesses (slower)

Mode 4: Register Addressing

Definition: The operand is in a CPU register. No memory access needed.

EA: None — operand is in the specified register.

REGISTER
  Instruction: [ OP | R3 ]
                      │
                      ▼
                 R3 = 42   ← Operand is in register R3

  Operand = R3 = 42
  Example: ADD R1, R3      → R1 = R1 + R3
  Use: Fastest operations, loop variables
  Speed: ★★★★★ No memory access

Mode 5: Register Indirect Addressing

Definition: The register contains the memory address of the operand.

EA = [Register] (contents of register is the address)

REGISTER INDIRECT
  Instruction: [ OP | R3 ]
                      │
                      ▼
                 R3 = 800   ← R3 holds memory address
                      │
                      ▼
               Memory[800] = 42   ← Actual operand

  EA = 800 (value in R3), Operand = 42
  Example: LOAD (R3)       → AC = M[R3] = M[800] = 42
  Use: Array access, pointer dereferencing
  Speed: ★★★★ One memory access

Mode 6: Autoincrement Addressing

Definition: Like register indirect, but the register is automatically incremented after use. Perfect for array traversal.

EA = [R]; then R ← R + 1

AUTOINCREMENT
  Before: R3 = 800

  Instruction: [ OP | (R3)+ ]
                      │
                 R3 = 800 → Memory[800] = 42   ← Operand
                      │
                 R3 = 801   ← R3 auto-incremented after access

  EA = 800, Operand = 42, R3 updated to 801
  Example: LOAD (R3)+      → AC = M[R3]; R3 = R3 + 1
  Use: Array traversal, sequential data processing
  Speed: ★★★★ One memory access + register update

Mode 7: Displacement (Indexed) Addressing

Definition: EA is computed by adding a constant displacement in the instruction to the contents of a register.

EA = Address field + [R]

DISPLACEMENT / INDEXED
  Instruction: [ OP | 100 | R2 ]
                      │      │
                      │   R2 = 500
                      │      │
                      └──+───┘
                         │
                    EA = 100 + 500 = 600
                         │
                  Memory[600] = 42   ← Operand

  EA = 600, Operand = 42
  Example: LOAD 100(R2)    → AC = M[100 + R2] = M[600] = 42
  Use: Accessing struct fields, array elements with base
  Speed: ★★★★ One addition + one memory access

Mode 8: Relative Addressing

Definition: EA is computed by adding the address field (offset) to the Program Counter (PC). Used for branch instructions.

EA = PC + Address field

RELATIVE
  Instruction at PC=200: [ OP | +50 ]
                                 │
                      PC = 200 + 50 = 250
                                 │
                          EA = 250 (target of branch)

  EA = 250
  Example: BEQ +50          → if zero flag set, jump to PC+50 = 250
  Use: Branch/jump instructions, position-independent code
  Speed: ★★★★ One addition (no memory access for address)

Comparison of All 8 Addressing Modes

5. RISC vs CISC Architecture

The two dominant CPU design philosophies are RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). This is one of the most important comparisons in computer architecture and a frequent GATE topic.

ARM (RISC) vs Intel x86 (CISC) — Real World

6. Data Transfer & Manipulation Instructions

Data Transfer Instructions

Data Manipulation Instructions

7. Program Control & Interrupts

Program Control Instructions

Interrupts

An interrupt is a signal that diverts the CPU from its current program to execute a special routine called an Interrupt Service Routine (ISR). After handling the interrupt, the CPU returns to the original program.

Interrupt Handling Cycle

INTERRUPT FLOW
  Program Execution
        │
        ▼
  ┌─────────────────┐
  │ Interrupt Signal │ ← Device sends interrupt request
  └────────┬────────┘
           ▼
  ┌─────────────────┐
  │ Finish Current  │ ← CPU completes current instruction
  │ Instruction     │
  └────────┬────────┘
           ▼
  ┌─────────────────┐
  │ Save Context    │ ← Push PC and PSW onto stack
  │ (PC, PSW, Regs) │
  └────────┬────────┘
           ▼
  ┌─────────────────┐
  │ Identify Source  │ ← Polling or vectored interrupt
  └────────┬────────┘
           ▼
  ┌─────────────────┐
  │ Load ISR Address │ ← From interrupt vector table
  │ into PC         │
  └────────┬────────┘
           ▼
  ┌─────────────────┐
  │ Execute ISR     │ ← Handle the interrupt
  └────────┬────────┘
           ▼
  ┌─────────────────┐
  │ RTI (Return     │ ← Pop PC and PSW from stack
  │ from Interrupt) │
  └────────┬────────┘
           ▼
  Resume Original Program

Priority Interrupt Systems

8. Processor Status Word (PSW) & Flags

The Processor Status Word (PSW), also called the Flags Register or EFLAGS (in x86), is a special register that holds condition codes set by ALU operations. These flags are used by conditional branch instructions to make decisions.

Trace: ADD 0x7FFF + 0x0001 (16-bit signed)

FLAG TRACE
  Operand A:  0x7FFF  =  0111 1111 1111 1111  (+32767, max positive 16-bit)
  Operand B:  0x0001  =  0000 0000 0000 0001  (+1)

  Binary Addition:
    0111 1111 1111 1111   (0x7FFF = +32767)
  + 0000 0000 0000 0001   (0x0001 = +1)
  ─────────────────────
    1000 0000 0000 0000   (0x8000 = -32768 in signed!)

  Result = 0x8000

  Flag Analysis:
  ┌──────┬────────┬──────────────────────────────────────────┐
  │ Flag │ Value  │ Reason                                   │
  ├──────┼────────┼──────────────────────────────────────────┤
  │  CF  │   0    │ No carry out of bit 15 (unsigned OK)     │
  │  ZF  │   0    │ Result ≠ 0                               │
  │  SF  │   1    │ MSB = 1 (result appears negative)        │
  │  OF  │   1    │ +ve + +ve = −ve → signed overflow!       │
  └──────┴────────┴──────────────────────────────────────────┘

  Explanation: Adding two positive numbers (0x7FFF + 0x0001) gave a
  negative result (0x8000 = -32768). This is SIGNED OVERFLOW.
  OF is set because the sign of the result doesn't match expected.
  CF is NOT set because there's no carry out in unsigned addition.

More Flag Trace Examples

Learn by Doing — 3-Tier Lab Structure

         ×
        / \
       +   +
      / \ / \
     A  B C  D

Python
class SimpleCPU:
    def __init__(self):
        self.registers = [0] * 8       # R0-R7
        self.memory = [0] * 256        # 256-word memory
        self.flags = {'CF':0, 'ZF':0, 'SF':0, 'OF':0}

    def load(self, reg, addr):
        # TODO: Load memory[addr] into registers[reg]
        pass

    def store(self, reg, addr):
        # TODO: Store registers[reg] into memory[addr]
        pass

    def add(self, dest, src1, src2):
        # TODO: registers[dest] = registers[src1] + registers[src2]
        # TODO: Update ZF, SF, CF, OF flags
        pass

    def display_state(self):
        # TODO: Print all register values and flags
        pass

Problem Bank — Diagrams, Numericals, Industry & GATE

Diagram-Based Problems (3)

Numerical Problems (6)

Industry Problems (3)

GATE-Style Problems (5)

MCQ Assessment Bank — 30 Questions (Bloom's Mapped)

Remember / Identify (Q1–Q5)

Understand / Explain (Q6–Q10)

Apply / Solve (Q11–Q15)

Analyze / Compare (Q16–Q20)

Evaluate / Justify (Q21–Q25)

Create / Design (Q26–Q30)

Short Answer Questions (8)

Long Answer Questions (3)

DATAPATH
  ┌──────────────────────────────────────────┐
  │          INSTRUCTION REGISTER            │
  │  [Opcode|  RD  |  RS1  |  RS2  ]        │
  │   6 bits  3 bits  3 bits  3 bits         │
  └────┬───────┬───────┬────────┬────────────┘
       │       │       │        │
       ▼       │       ▼        ▼
  ┌─────────┐  │  ┌──────────────────┐
  │ Control │  │  │   REGISTER FILE  │
  │  Unit   │  │  │  Read Port A←RS1 │──→ Bus A
  │         │  │  │  Read Port B←RS2 │──→ Bus B
  │ ALU_OP  │  │  │  Write Port←RD   │←── Result Bus
  │ RegWrite│  │  │  Write Enable    │←── RegWrite
  └────┬────┘  │  └──────────────────┘
       │       │           │         │
       │       │      Bus A│    Bus B│
       ▼       │           ▼         ▼
       │       │     ┌─────────────────┐
       ├───────┼────→│      A L U      │
       │       │     │  (ALU_OP input)  │
       │       │     └───────┬─────────┘
       │       │             │ Result
       │       │             ▼
       │       │     ┌───────────────┐
       │       │     │  FLAGS (PSW)  │
       │       │     │ CF ZF SF OF   │
       │       └─────┤  Result Bus   │──→ back to Register File
       │             └───────────────┘

Industry Spotlight — A Day in the Life

Earn With It — Embedded Projects & CPU Design

Chapter Summary

Key Formulas for Quick Revision

Earning Checkpoint

✅ Unit 4 complete. Ready for Unit 5: Pipeline & Vector Processing!

[QR: Link to EduArtha video tutorial — Central Processing Unit]