Computer Organization & Architecture

Unit 3: Computer Organization

From instruction codes to interrupt handling — master Mano's Basic Computer architecture, the common bus system, and the complete instruction cycle used in every modern processor.

⏱️ 7 hrs theory + 5 hrs lab | 🎯 GATE ~4 marks | 🖥️ Mano's Basic Computer

💼 Jobs this unlocks: Hardware Design Engineer (₹6–10 LPA) | VLSI Engineer (₹8–15 LPA) | Embedded Systems (₹5–9 LPA)

Section A

Opening Hook — The Brain Inside Your Phone

🏢 Qualcomm Snapdragon 8 Gen 3 — The ₹80,000-Crore Bus Architecture in Your Pocket

When you unlock your OnePlus 12 or Samsung Galaxy S24 Ultra, a marvel of computer organization springs to life. The Qualcomm Snapdragon 8 Gen 3 chip inside contains over 20 billion transistors on a die smaller than your fingernail. But raw transistors are useless without organisation — how data moves between the CPU cores, memory, GPU, and I/O peripherals.

At the heart of this chip lies a bus architecture — a set of shared communication pathways that connect the Kryo CPU cores, the Adreno 750 GPU, the Hexagon DSP, and LPDDR5X memory. Every instruction you trigger — opening Instagram, running a BGMI match, scanning a UPI QR code — travels through this bus system at speeds exceeding 4 GHz. The bus must arbitrate: Who gets to talk? In what order? How does the CPU fetch the next instruction while the GPU renders a frame?

This chapter teaches you exactly how a computer is organised internally — using Mano's Basic Computer as the foundational model. Every concept here — registers, buses, instruction cycles, interrupts — maps directly to what happens inside that Snapdragon chip. Understanding this is the difference between a coder and a computer engineer.

🇮🇳 Qualcomm India (Hyderabad)🇮🇳 Samsung R&D (Bangalore)🇮🇳 ARM India (Bangalore)🇮🇳 Intel India (Bangalore)🇮🇳 MediaTek India🇮🇳 ISRO (Ahmedabad)

India is the world's #2 chip design hub. Qualcomm's Hyderabad centre designed critical components of the Snapdragon 8 Gen 3's bus interconnect. Over 20,000 chip designers in India work on processor organisation — the exact topic of this chapter. GATE COA questions worth ~4 marks come directly from Mano's Basic Computer topics covered here.

Section B

Learning Outcomes — Bloom's Taxonomy Mapped (12 Outcomes)

Bloom's Level	Learning Outcome
🔵 Remember	LO1: List all 8 registers of Mano's Basic Computer with their bit-widths and functions
🔵 Remember	LO2: State the 16-bit instruction format: I(1) + Opcode(3) + Address(12) and recall all 7 memory-reference opcodes
🟢 Understand	LO3: Explain how the common bus system uses MUX selection lines S₂S₁S₀ to route data between registers
🟢 Understand	LO4: Describe the Fetch-Decode-Execute cycle with timing signals T₀, T₁, T₂ and their micro-operations
🟡 Apply	LO5: Trace the complete execution of any memory-reference instruction (AND, ADD, LDA, STA, BUN, BSA, ISZ) through all timing states
🟡 Apply	LO6: Write RTL (Register Transfer Language) micro-operations for each instruction and timing signal
🟠 Analyze	LO7: Compare hardwired vs microprogrammed control units — speed, flexibility, complexity, and use cases
🟠 Analyze	LO8: Analyze the interrupt cycle and determine how IEN, FGI, FGO flags interact to handle I/O
🔴 Evaluate	LO9: Evaluate design trade-offs in bus width, register count, and instruction format for a basic CPU
🔴 Evaluate	LO10: Justify why Mano's 25-instruction architecture is sufficient to demonstrate Turing-completeness
🟣 Create	LO11: Design a simple CPU simulator that implements the fetch-decode-execute cycle for Mano's instructions
🟣 Create	LO12: Construct timing diagrams and control signal tables for a new custom instruction added to Mano's ISA

Section C

Concept Explanation — Mano's Basic Computer from Scratch

1. Instruction Codes

Every computer instruction is a binary code that tells the CPU what to do and where to find data. In Mano's Basic Computer, instructions are exactly 16 bits long.

📐 16-Bit Mano Instruction Format

  15   14  13  12   11                          0
┌────┬────┬────┬────┬────────────────────────────┐
│  I │    Opcode    │        Address (12 bits)    │
│    │  (3 bits)    │                             │
└────┴────┴────┴────┴────────────────────────────┘
  ↑        ↑                    ↑
  │        │                    └── Memory address (0–4095)
  │        └── Operation code (0–7)
  └── Addressing mode: 0 = Direct, 1 = Indirect

Bit 15 (I): The indirect addressing bit. When I = 0, the address field directly points to the operand. When I = 1, the address field points to a memory location that contains the actual operand address.

Bits 14–12 (Opcode): 3 bits = 8 possible opcodes (0–7). Seven are memory-reference instructions; opcode 111 is used for register-reference and I/O instructions.

Bits 11–0 (Address): 12 bits = 2¹² = 4096 addressable memory locations (4K words).

Opcode Table — The 7 Memory-Reference Instructions

Opcode (Hex)	Symbol	Operation	RTL Description
0x0 (000)	`AND`	Bitwise AND	AC ← AC ∧ M[effective address]
0x1 (001)	`ADD`	Add to AC	AC ← AC + M[effective address], E ← carry
0x2 (010)	`LDA`	Load to AC	AC ← M[effective address]
0x3 (011)	`STA`	Store AC	M[effective address] ← AC
0x4 (100)	`BUN`	Branch Unconditionally	PC ← effective address
0x5 (101)	`BSA`	Branch and Save Return	M[effective address] ← PC, PC ← effective address + 1
0x6 (110)	`ISZ`	Increment and Skip if Zero	M[effective address] ← M[effective address] + 1; if result = 0, PC ← PC + 1

Mnemonic trick for opcodes: All Adding Ladies Should Bring Beautiful Items → AND, ADD, LDA, STA, BUN, BSA, ISZ (opcodes 0–6 in order). This appears in GATE questions every year!

Direct vs Indirect Addressing — The Courier Analogy:

Direct (I=0): You give a courier the address "Flat 301, Tower B." He goes straight there. The address in the instruction IS the location of the data.

Indirect (I=1): You give a courier the address "Go to the security desk." The security desk has a chit saying "Flat 301, Tower B." The courier goes to the desk first, reads the chit, then goes to the flat. The instruction points to a place that holds the actual address.

Students confuse opcode 111 (7) with memory-reference instructions. When opcode = 111, the instruction is NOT a memory-reference instruction. If I=0, it's a register-reference instruction. If I=1, it's an I/O instruction. The 12-bit address field now becomes individual operation bits, not a memory address.

2. Computer Registers

Registers are the fastest storage inside the CPU — like Post-it notes on your desk versus a filing cabinet across the room (RAM). Mano's Basic Computer has 8 registers:

🗄️ Register Set of Mano's Basic Computer

┌─────────────────────────────────────────────────────────────┐
│                  MANO'S BASIC COMPUTER REGISTERS            │
├──────────┬──────┬───────────────────────────────────────────┤
│ Register │ Bits │ Function                                  │
├──────────┼──────┼───────────────────────────────────────────┤
│ PC       │  12  │ Program Counter — next instruction addr   │
│ AR       │  12  │ Address Register — holds memory address   │
│ IR       │  16  │ Instruction Register — current instruction│
│ AC       │  16  │ Accumulator — main data register, ALU     │
│ DR       │  16  │ Data Register — operand from memory       │
│ TR       │  16  │ Temporary Register — temp storage         │
│ INPR     │   8  │ Input Register — keyboard input char      │
│ OUTR     │   8  │ Output Register — display output char     │
├──────────┼──────┼───────────────────────────────────────────┤
│ E        │   1  │ Carry flip-flop (overflow from AC)        │
├──────────┼──────┼───────────────────────────────────────────┤
│ Memory   │  16  │ 4096 words × 16 bits = 4K × 16           │
└──────────┴──────┴───────────────────────────────────────────┘

Why 12-bit PC and AR? Because the address field is 12 bits, addressing 2¹² = 4096 locations. The PC and AR only need to hold addresses, so 12 bits suffice.

Why 16-bit AC, DR, IR, TR? Because the memory word size is 16 bits. Data and instructions are both 16 bits wide, so these registers match.

Why 8-bit INPR and OUTR? Because I/O devices (keyboard, printer) use ASCII characters, which are 8 bits (0–255).

Think of registers like the counters at an Indian railway station: PC is the queue number display (tells which passenger/instruction is next). AR is the "Go to Window 5" direction (address to access). IR is the form you fill (the instruction being processed). AC is the cashier's drawer (where computation happens). DR is the customer's wallet (brings data). INPR is the microphone (input device). OUTR is the speaker (output device).

3. Common Bus System

The common bus is a shared highway that connects all registers and memory. Only one register can put data on the bus at a time. A multiplexer (MUX) controlled by three selection lines S₂S₁S₀ decides who gets to "drive" the bus.

🔀 Common Bus System — Full Architecture

         S₂ S₁ S₀  (Bus Select Lines from Control Unit)
          │  │  │
          ▼  ▼  ▼
    ┌─────────────────┐
    │   16-bit MUX    │ ◄── Selects which register outputs to bus
    │  (Multiplexer)  │
    └────────┬────────┘
             │
             ▼
    ╔════════════════════════════════════════════╗
    ║          16-BIT COMMON BUS                 ║
    ╚════════════════════════════════════════════╝
      │      │      │      │      │      │      │
      ▼      ▼      ▼      ▼      ▼      ▼      ▼
   ┌─────┐┌─────┐┌─────┐┌─────┐┌─────┐┌─────┐┌──────┐
   │ AR  ││ PC  ││ DR  ││ AC  ││ IR  ││ TR  ││Memory│
   │[12] ││[12] ││[16] ││[16] ││[16] ││[16] ││[4K×16]│
   └─────┘└─────┘└─────┘└─────┘└─────┘└─────┘└──────┘

  ┌──────────────────────────────────────────────────┐
  │         MUX SELECT LINE ENCODING                 │
  ├─────────┬────────────────────────────────────────┤
  │ S₂S₁S₀  │  Register on Bus                      │
  ├─────────┼────────────────────────────────────────┤
  │  0 0 1  │  AR  (Address Register)                │
  │  0 1 0  │  PC  (Program Counter)                 │
  │  0 1 1  │  DR  (Data Register)                   │
  │  1 0 0  │  AC  (Accumulator)                     │
  │  1 0 1  │  IR  (Instruction Register)            │
  │  1 1 0  │  TR  (Temporary Register)              │
  │  1 1 1  │  Memory (M[AR])                        │
  │  0 0 0  │  None (bus idle)                       │
  └─────────┴────────────────────────────────────────┘

  Data Flow Example:  DR ← M[AR]
  ─────────────────────────────
  1. Control sets S₂S₁S₀ = 111 (Memory on bus)
  2. Memory reads word at address in AR
  3. Data appears on common bus
  4. DR load signal is activated
  5. DR latches the data from bus

Analogy — Delhi Metro Shared Track: Think of the common bus as a Delhi Metro line. Only one train (register data) can use a track segment at a time. The signalling system (S₂S₁S₀) decides which train goes next. If two trains try to use the same track — collision! Similarly, if two registers drive the bus simultaneously — data corruption!

Bus ≠ multiple parallel connections. A common bus is a SHARED medium. Students often draw it as separate wires from each register to every other register. In reality, there is ONE set of 16 wires, and a MUX decides who outputs to them. This saves enormous wiring compared to point-to-point connections (which would need n(n-1)/2 connections for n registers).

4. Computer Instructions

Mano's Basic Computer has exactly 25 instructions divided into three categories:

📋 Complete Instruction Set — Three Categories

Category 1: Memory-Reference Instructions (7 instructions)

These use a 12-bit address to access memory. Opcode = 000 to 110. I bit determines direct/indirect.

Symbol	Opcode	Description
AND	000	AND memory word to AC
ADD	001	Add memory word to AC
LDA	010	Load memory word to AC
STA	011	Store AC in memory
BUN	100	Branch unconditionally
BSA	101	Branch and save return address
ISZ	110	Increment and skip if zero

Category 2: Register-Reference Instructions (12 instructions)

Opcode = 111, I = 0. The 12-bit field specifies the operation (only one bit is set).

Hex Code	Symbol	Description
7800	CLA	Clear AC
7400	CLE	Clear E (carry flip-flop)
7200	CMA	Complement AC
7100	CME	Complement E
7080	CIR	Circular right shift AC and E
7040	CIL	Circular left shift AC and E
7020	INC	Increment AC
7010	SPA	Skip if AC positive (AC₁₅ = 0)
7008	SNA	Skip if AC negative (AC₁₅ = 1)
7004	SZA	Skip if AC zero
7002	SZE	Skip if E is zero
7001	HLT	Halt the computer

Category 3: I/O Instructions (6 instructions)

Opcode = 111, I = 1. Used for input/output and interrupt control.

Hex Code	Symbol	Description
F800	INP	Input character to AC(0–7)
F400	OUT	Output character from AC(0–7)
F200	SKI	Skip if input flag FGI = 1
F100	SKO	Skip if output flag FGO = 1
F080	ION	Interrupt enable on (IEN ← 1)
F040	IOF	Interrupt enable off (IEN ← 0)

25 instructions are enough to compute anything! Mano's Basic Computer with just 25 instructions is Turing-complete — meaning it can theoretically compute anything that any modern computer can, given enough time and memory. Your Snapdragon has billions of transistors, but the fundamental principle is the same.

5. Timing and Control

The control unit is the "brain of the brain" — it generates signals that tell every other component what to do and when. There are two fundamentally different approaches:

Approach 1: Hardwired Control Unit

⚡ Hardwired Control — Speed at the Cost of Flexibility

  ┌────────────────────────────────────────────────┐
  │              HARDWIRED CONTROL UNIT             │
  │                                                 │
  │  ┌────────┐     ┌──────────────┐    ┌────────┐ │
  │  │  IR    │────▶│   Decoder    │───▶│ Control│ │
  │  │(opcode)│     │  (3×8 dec)   │    │ Logic  │ │
  │  └────────┘     └──────────────┘    │(gates) │ │
  │                                      │        │ │
  │  ┌────────┐     ┌──────────────┐    │        │ │
  │  │Sequence│────▶│   Decoder    │───▶│        │ │
  │  │Counter │     │  (4×16 dec)  │    │        │ │
  │  │ (SC)   │     │  T₀,T₁...T₁₅│    │        │ │
  │  └────────┘     └──────────────┘    └───┬────┘ │
  │                                          │      │
  │         ┌────────────────────────────────┘      │
  │         ▼                                       │
  │  Control Signals: Load, Clear, Increment,      │
  │  Read, Write, MUX select (S₂S₁S₀), ALU op     │
  └────────────────────────────────────────────────┘

  How it works:
  ─────────────
  • Instruction opcode bits from IR are decoded (3-to-8 decoder)
  • Sequence counter SC provides timing signals T₀, T₁, T₂...
  • Combinational logic gates combine decoded signals + timing
    to produce exact control signals at each clock cycle
  • SC increments each clock: T₀ → T₁ → T₂ → ...
  • After instruction completes, SC is cleared back to T₀

Approach 2: Microprogrammed Control Unit

🧬 Microprogrammed Control — Flexibility at the Cost of Speed

  ┌────────────────────────────────────────────────┐
  │          MICROPROGRAMMED CONTROL UNIT           │
  │                                                 │
  │  ┌────────┐    ┌────────────────────┐           │
  │  │  IR    │───▶│  Mapping Logic     │           │
  │  │(opcode)│    │  (opcode→µaddr)    │           │
  │  └────────┘    └────────┬───────────┘           │
  │                         │                        │
  │                         ▼                        │
  │              ┌──────────────────┐                │
  │              │  Control Address │                │
  │              │  Register (CAR)  │                │
  │              └────────┬─────────┘                │
  │                       │                          │
  │                       ▼                          │
  │  ┌─────────────────────────────────────┐        │
  │  │       CONTROL MEMORY (ROM)          │        │
  │  │  ┌───────────────────────────────┐  │        │
  │  │  │ µAddress │ Control │ Next Addr│  │        │
  │  │  │          │  Word   │  Field   │  │        │
  │  │  │──────────┼─────────┼──────────│  │        │
  │  │  │  0x00    │ 01010.. │  0x01    │  │        │
  │  │  │  0x01    │ 11001.. │  0x02    │  │        │
  │  │  │  0x02    │ 00110.. │  0x00    │  │        │
  │  │  │   ...    │   ...   │   ...    │  │        │
  │  │  └───────────────────────────────┘  │        │
  │  └──────────────────────┬──────────────┘        │
  │                         │                        │
  │                         ▼                        │
  │                  Control Signals                 │
  └────────────────────────────────────────────────┘

  How it works:
  ─────────────
  • Each machine instruction maps to a sequence of µ-instructions
  • µ-instructions stored in Control Memory (ROM)
  • Each µ-instruction word contains control signal bits
  • CAR sequences through µ-instructions automatically
  • To change CPU behavior, just reprogram the ROM!

Comparison Table: Hardwired vs Microprogrammed

Feature	Hardwired	Microprogrammed
Speed	Faster (direct gate logic)	Slower (ROM lookup each cycle)
Flexibility	Inflexible — redesign gates to modify	Flexible — just update ROM contents
Cost	Expensive for complex ISAs	Cheaper for complex ISAs
Design Complexity	High (boolean equations grow exponentially)	Lower (systematic tabular approach)
Used In	RISC CPUs (ARM, MIPS)	CISC CPUs (x86, VAX)
Bug Fixing	Requires physical redesign	Microcode patch (Intel does this!)
Example	Mano's Basic Computer	Intel Pentium, IBM System/360
GATE Questions	Frequently asked	Comparison questions common

Qualcomm's Snapdragon uses hardwired control for its ARM Cortex cores (RISC architecture — simple, fast instructions). But Intel's Core i7 (used in many Indian office PCs and data centres) uses microprogrammed control for its complex x86 CISC architecture. When Intel discovers a CPU bug (like Spectre/Meltdown in 2018), they push a microcode update — literally reprogramming the control memory via a software patch!

6. Instruction Cycle — Fetch-Decode-Execute

Every instruction goes through a three-phase cycle. Think of it as the heartbeat of the CPU — it repeats for every single instruction, billions of times per second in modern processors.

🔄 Fetch-Decode-Execute State Diagram

  START
    │
    ▼
┌──────────────────────────────────────────────────┐
│  T₀: FETCH Phase — Step 1                        │
│  ┌─────────────────────────────────┐             │
│  │  AR ← PC                       │             │
│  │  (Put PC address into AR)       │             │
│  └─────────────────────────────────┘             │
│  Bus: S₂S₁S₀ = 010 (PC on bus), AR load         │
└──────────────────────┬───────────────────────────┘
                       │
                       ▼
┌──────────────────────────────────────────────────┐
│  T₁: FETCH Phase — Step 2                        │
│  ┌─────────────────────────────────┐             │
│  │  IR ← M[AR],  PC ← PC + 1     │             │
│  │  (Read instruction from memory) │             │
│  │  (Increment PC to next addr)    │             │
│  └─────────────────────────────────┘             │
│  Bus: S₂S₁S₀ = 111 (Memory on bus), IR load     │
│  PC increment signal activated simultaneously    │
└──────────────────────┬───────────────────────────┘
                       │
                       ▼
┌──────────────────────────────────────────────────┐
│  T₂: DECODE Phase                                │
│  ┌─────────────────────────────────┐             │
│  │  Decode IR(14–12) → opcode      │             │
│  │  AR ← IR(11–0)                  │             │
│  │  Determine: I, D₀–D₇            │             │
│  └─────────────────────────────────┘             │
│  3×8 Decoder produces D₀–D₇ from opcode bits    │
│  I = IR(15), decides direct/indirect             │
└──────────────────────┬───────────────────────────┘
                       │
            ┌──────────┴──────────┐
            │                     │
     ┌──────▼──────┐      ┌──────▼──────┐
     │ D₇'I (D₇=0)│      │ D₇ (D₇=1)  │
     │ Memory-Ref  │      │ Reg/IO Ref  │
     │ Instruction │      │ Instruction │
     └──────┬──────┘      └──────┬──────┘
            │                     │
     ┌──────▼──────┐      ┌──────▼──────┐
     │ T₃: Check I │      │ T₃: Execute│
     │ If I=1:     │      │ directly   │
     │ AR←M[AR]    │      │ (one cycle)│
     │(indirect)   │      │ SC←0       │
     └──────┬──────┘      └────────────┘
            │
     ┌──────▼──────┐
     │T₄–T₆:      │
     │EXECUTE Phase│
     │(varies by   │
     │ instruction)│
     │ SC ← 0      │
     └─────────────┘

Analogy: Instruction Cycle = IRCTC Train Booking

T₀ (Fetch-1): You open IRCTC and type the train number (AR ← PC — you tell the system which record to look up).
T₁ (Fetch-2): IRCTC retrieves the train details (IR ← M[AR] — read instruction from memory). You automatically move to the next step (PC++).
T₂ (Decode): You read the form — is this a booking? Cancellation? Tatkal? (Decode opcode). You also note the PNR/address details (AR ← IR address).
T₃ (Indirect?): If it says "see agent for details," you first go to the agent (indirect addressing) before proceeding.
T₄+ (Execute): You actually click "Book" or "Cancel" — the real work happens. After completion, you go back to start for the next operation (SC ← 0).

Every train booking follows this cycle. Every CPU instruction follows this cycle. Billions of times per second.

7. Memory-Reference Instructions — Complete Micro-operations

Each memory-reference instruction executes after the fetch and decode phases (T₀–T₂). If indirect addressing (I=1), T₃ resolves the effective address. The actual operation happens at T₄ (or T₃ for direct).

🔧 All 7 Memory-Reference Micro-operations

AND (Opcode 000) — D₀T₅

D₀T₄: DR ← M[AR]        // Read operand from memory
D₀T₅: AC ← AC ∧ DR,     // Bitwise AND with accumulator
       SC ← 0            // Clear sequence counter

ADD (Opcode 001) — D₁T₅

D₁T₄: DR ← M[AR]        // Read operand from memory
D₁T₅: AC ← AC + DR,     // Add operand to accumulator
       E ← Cout,         // Carry goes to E flip-flop
       SC ← 0            // Clear sequence counter

LDA (Opcode 010) — D₂T₅

D₂T₄: DR ← M[AR]        // Read operand from memory
D₂T₅: AC ← DR,          // Load data into accumulator
       SC ← 0            // Clear sequence counter

STA (Opcode 011) — D₃T₄

D₃T₄: M[AR] ← AC,       // Store accumulator to memory
       SC ← 0            // Clear sequence counter

BUN (Opcode 100) — D₄T₄

D₄T₄: PC ← AR,          // Set PC to branch address
       SC ← 0            // Clear sequence counter

BSA (Opcode 101) — D₅T₅

D₅T₄: M[AR] ← PC,       // Save return address
       AR ← AR + 1       // Point to next location
D₅T₅: PC ← AR,          // Jump to subroutine
       SC ← 0            // Clear sequence counter

ISZ (Opcode 110) — D₆T₆

D₆T₄: DR ← M[AR]        // Read memory word
D₆T₅: DR ← DR + 1       // Increment the word
D₆T₆: M[AR] ← DR,       // Write back to memory
       if (DR = 0) then PC ← PC + 1,  // Skip next if zero
       SC ← 0            // Clear sequence counter

📝 Execution Trace: ADD Instruction

Let's trace ADD 200 (direct addressing). Assume: PC=100, M[100]=1200₁₆ (ADD instruction with address 200), M[200]=0005₁₆, AC=0003₁₆

Time	Micro-operation	AR	IR	DR	AC	PC	Bus
T₀	AR ← PC	100	—	—	0003	100	PC→Bus→AR
T₁	IR ← M[AR], PC++	100	1200	—	0003	101	M→Bus→IR
T₂	Decode, AR ← IR(0–11)	200	1200	—	0003	101	IR→Bus→AR
T₃	I=0, D₁=1 (ADD)	200	1200	—	0003	101	—
T₄	DR ← M[AR]	200	1200	0005	0003	101	M→Bus→DR
T₅	AC ← AC+DR, SC←0	200	1200	0005	0008	101	ALU op

Result: AC = 0003 + 0005 = 0008. E = 0 (no carry). PC = 101 (ready for next instruction).

GATE Tip: The trace table is a gold mine. You'll be asked: "After executing ADD 200, what is the value in AC?" — just trace through T₀ to T₅ systematically. Write the table on rough paper during the exam. It prevents silly mistakes that cost 2 marks.

8. I/O and Interrupt

The CPU is millions of times faster than I/O devices (keyboard, printer). If the CPU waited for every keypress, it would waste 99.99% of its time doing nothing. The solution: interrupts.

📡 I/O System — Registers and Flags

  ┌────────────────────────────────────────────────┐
  │              I/O SYSTEM REGISTERS               │
  │                                                 │
  │  ┌──────────┐          ┌──────────┐            │
  │  │  INPR    │          │  OUTR    │            │
  │  │ (8 bits) │          │ (8 bits) │            │
  │  │ Keyboard │          │ Display  │            │
  │  └────┬─────┘          └────┬─────┘            │
  │       │                     │                   │
  │  ┌────▼─────┐          ┌────▼─────┐            │
  │  │ FGI      │          │ FGO      │            │
  │  │ (1 bit)  │          │ (1 bit)  │            │
  │  │ Input    │          │ Output   │            │
  │  │ Flag     │          │ Flag     │            │
  │  └──────────┘          └──────────┘            │
  │                                                 │
  │  FGI = 1 → New character ready in INPR         │
  │  FGI = 0 → No new input yet                    │
  │  FGO = 1 → Output device ready for new char    │
  │  FGO = 0 → Device busy, wait                   │
  │                                                 │
  │  ┌──────────┐                                  │
  │  │ IEN      │  Interrupt Enable (1 bit)        │
  │  │ (1 bit)  │  1 = interrupts allowed          │
  │  └──────────┘  0 = interrupts disabled          │
  └────────────────────────────────────────────────┘

FGI (Input Flag): When you press a key, the keyboard controller sets FGI = 1 and loads the ASCII code into INPR. The CPU can then read INPR and clear FGI.

FGO (Output Flag): When the display finishes printing a character, it sets FGO = 1, signalling "I'm ready for the next character." The CPU loads OUTR and clears FGO.

IEN (Interrupt Enable): A master switch. If IEN = 0, the CPU ignores all I/O flags. If IEN = 1, the CPU checks FGI and FGO between instructions.

The Interrupt Cycle

🚨 Interrupt Handling — Step by Step

  After EXECUTE phase, before next FETCH:
  ──────────────────────────────────────────

  Check: Is (IEN = 1) AND (FGI = 1 OR FGO = 1)?

      NO → Continue with next Fetch (T₀)
      YES → Enter INTERRUPT CYCLE:

  ┌─────────────────────────────────────────────────┐
  │  INTERRUPT CYCLE (happens at T₀, T₁, T₂)       │
  │                                                  │
  │  T₀: AR ← 0, TR ← PC                           │
  │      (Save current PC, set AR to address 0)     │
  │                                                  │
  │  T₁: M[0] ← TR, PC ← 0                         │
  │      (Store return address at M[0])              │
  │      (Set PC to address 0)                       │
  │                                                  │
  │  T₂: PC ← PC + 1, IEN ← 0, SC ← 0             │
  │      (PC now = 1 → jump to ISR at address 1)    │
  │      (Disable interrupts to prevent nesting)     │
  │      (Clear SC for next fetch)                   │
  └─────────────────────────────────────────────────┘

  After interrupt cycle:
  • PC = 1, so next instruction fetched from address 1
  • Address 1 contains: BUN [ISR address]
  • ISR (Interrupt Service Routine) handles the I/O
  • ISR ends with: ION (re-enable interrupts)
  •                BUN 0 I (indirect: jump to M[0] = return addr)

Analogy — Interrupts = Doorbell while cooking: You're cooking biryani (executing instructions). The doorbell rings (FGI = 1 — input ready). If you've told your family "don't disturb" (IEN = 0), you ignore it. But if IEN = 1, you note your recipe step (save PC), go answer the door (jump to ISR), handle the visitor, then return to cooking from where you left off (restore PC).

Students forget that IEN is cleared during the interrupt cycle. This is crucial — it prevents a second interrupt from interrupting the ISR (no nested interrupts in Mano's basic model). The ISR must explicitly re-enable interrupts with ION before returning.

Section D

Learn by Doing — 3-Tier Lab Structure

🟢 Tier 1 — GUIDED: Trace an ADD Instruction on Paper

⏱️ 45–60 minutesBeginnerZero prior knowledge assumed

Step 1: Set Up the Initial State

Draw this table on paper (or in a spreadsheet):

Register	Initial Value
PC	050 (hex)
AC	000A (hex) = 10 in decimal
M[050]	1080 (hex) → ADD 080 direct
M[080]	0014 (hex) = 20 in decimal

Step 2: Decode the Instruction Manually

M[050] = 1080₁₆ = 0001 0000 1000 0000₂

Bit 15 (I) = 0 → Direct addressing

Bits 14–12 (Opcode) = 001 → ADD

Bits 11–0 (Address) = 000010000000 = 080₁₆

Step 3: Trace Through Each Timing Signal

Fill in this trace table row by row:

Time	Operation	AR	IR	DR	AC	PC
T₀	AR ← PC	050	—	—	000A	050
T₁	IR ← M[AR], PC++	050	1080	—	000A	051
T₂	Decode, AR ← 080	080	1080	—	000A	051
T₃	I=0, nothing extra	080	1080	—	000A	051
T₄	DR ← M[080]	080	1080	0014	000A	051
T₅	AC ← AC+DR	080	1080	0014	001E	051

✅ AC = 000A + 0014 = 001E (30 decimal). PC = 051 (next instruction).

Step 4: Now Try LDA 080

Change M[050] to 2080₁₆ (LDA 080). Reset AC to 000A. Trace it yourself. The answer should be AC = 0014.

Self-check: Try tracing STA 080 with AC = 00FF. What changes in memory after execution?

🟡 Tier 2 — SEMI-GUIDED: Build a CPU Simulator in Python

⏱️ 90–120 minutesIntermediateBasic Python required

Your Mission:

Build a Python program that simulates Mano's Basic Computer. It should:

Store a small program in a simulated 4096-word memory array
Implement the fetch-decode-execute cycle
Support at least: LDA, STA, ADD, AND, BUN, HLT
Print the trace table after each instruction

Skeleton Code (fill the gaps):

Python
# Mano's Basic Computer Simulator — Skeleton
memory = [0] * 4096   # 4K × 16-bit words
PC = 0; AC = 0; DR = 0; AR = 0; IR = 0; E = 0
running = True

# Load a test program
memory[0] = 0x2004   # LDA 004 (load M[004] into AC)
memory[1] = 0x1005   # ADD 005 (add M[005] to AC)
memory[2] = 0x3006   # STA 006 (store AC to M[006])
memory[3] = 0x7001   # HLT
memory[4] = 25        # Data: 25
memory[5] = 37        # Data: 37
memory[6] = 0         # Result location

while running:
    # T0: AR ← PC
    AR = PC
    # T1: IR ← M[AR], PC++
    IR = memory[AR]
    PC = (PC + 1) & 0xFFF
    # T2: Decode
    I = (IR >> 15) & 1
    opcode = (IR >> 12) & 7
    addr = IR & 0xFFF
    AR = addr

    # TODO: Handle indirect addressing (if I==1 and opcode!=7)
    # TODO: Implement each opcode
    # TODO: Print trace table row

print(f"Result at M[006]: {memory[6]}")
# Expected: 62 (25 + 37)

Stretch Goal: Add BSA (subroutine call) and BUN (unconditional jump) support. Write a program that adds three numbers using a subroutine.

🔴 Tier 3 — OPEN CHALLENGE: Visual CPU Simulator in HTML/JS

⏱️ 3–5 hoursAdvancedNo instructions — real-world mini-project

The Brief:

Build an interactive web-based CPU simulator for Mano's Basic Computer. Features:

Visual register display (PC, AR, IR, AC, DR, TR) with live values
Memory table showing all loaded words
"Step" button — advances one timing signal at a time (T₀, T₁, ...)
"Run" button — executes until HLT
Common bus animation showing data flow between registers
Instruction decode panel showing opcode, I-bit, and address in real-time
Support all 25 Mano instructions

Deliverable: A single HTML file with embedded CSS/JS. Host it on GitHub Pages for your portfolio.

CPU simulators are portfolio gold. Embedded systems companies in India (Qualcomm, Samsung R&D, TI India) actively look for candidates who demonstrate understanding of computer organisation through projects. A visual CPU simulator on your GitHub will make you stand out in VLSI and embedded job interviews.

Section E

Practice Problems — Diagrams, Numericals, Industry & GATE

Diagram Questions (3)

Draw the complete common bus system of Mano's Basic Computer showing all 7 registers, MUX, bus, and selection lines S₂S₁S₀. Label each register with its bit-width.

ApplyIntermediate

Refer to the ASCII diagram in Section C.3. Key points: (1) 16-bit bus, (2) 7 inputs to MUX including Memory, (3) S₂S₁S₀ select lines from control unit, (4) AR and PC are 12-bit (zero-extended on bus), (5) INPR and OUTR are NOT on the common bus (they connect through AC).

Draw the block diagram of a hardwired control unit showing: Instruction Register, opcode decoder, sequence counter, timing decoder, and control logic gates. Show how D₀–D₇ and T₀–T₁₅ signals are generated.

ApplyAdvanced

Key blocks: IR(14–12) → 3×8 Decoder → D₀–D₇. SC(4-bit) → 4×16 Decoder → T₀–T₁₅. Control logic takes D₀–D₇, T₀–T₁₅, I bit, and condition flags as inputs. Outputs are control signals for every register (Load, Clear, Increment), bus select lines, and memory Read/Write.

Draw the flowchart for the complete interrupt cycle showing the condition check (IEN, FGI, FGO), the three micro-operations at T₀, T₁, T₂, and the return mechanism.

ApplyIntermediate

Flowchart starts with decision diamond: "IEN=1 AND (FGI=1 OR FGO=1)?". If NO → proceed to T₀ of next fetch. If YES → T₀: AR←0, TR←PC. T₁: M[0]←TR, PC←0. T₂: PC←PC+1, IEN←0, SC←0. Then normal fetch begins from PC=1.

Numerical Questions (6)

The instruction at address 100₁₆ is 0x9200. What operation does it perform? Is it direct or indirect? What is the effective address?

ApplyBeginner

0x9200 = 1001 0010 0000 0000₂. I=1 (indirect). Opcode=001 (ADD). Address=0x200. Since I=1, effective address = M[0x200]. This is an indirect ADD: AC ← AC + M[M[0x200]].

Trace the execution of AND 0x050 (direct) with AC = 0xFF0F and M[050] = 0x0F0F. Show all timing signals T₀ through T₅ and the final value of AC.

ApplyIntermediate

T₀: AR←PC. T₁: IR←M[AR], PC++. T₂: Decode AND, AR←050. T₃: D₀=1, I=0. T₄: DR←M[050]=0x0F0F. T₅: AC ← 0xFF0F AND 0x0F0F = 0x0F0F. Only bits that are 1 in BOTH operands survive.

If PC = 300₁₆ and the instruction at 300 is BSA 400 (direct), what values are in PC, M[400], and where does execution continue after BSA completes?

AnalyzeIntermediate

After fetch, PC = 301. BSA execution: T₄: M[400] ← PC = 301 (return address saved), AR ← 401. T₅: PC ← AR = 401. So M[400] = 0x0301, PC = 0x401. Execution continues from address 401 (first instruction of subroutine).

An ISZ instruction targets address 0x100. M[100] currently holds 0xFFFF. After ISZ executes, what is M[100]? Does the CPU skip the next instruction?

ApplyIntermediate

ISZ: DR ← M[100] = 0xFFFF. DR ← DR+1 = 0x0000 (overflow wraps to zero). M[100] ← 0x0000. Since DR = 0, YES, PC ← PC+1 (skip next instruction). ISZ is typically used for loop counting: start with negative count, increment each iteration, skip when it reaches zero.

Calculate the total number of control signals needed for the common bus system. Consider: 7 register load signals, 3 bus select lines, memory read/write, ALU operations, and register clear/increment signals.

AnalyzeAdvanced

Load signals: AR, PC, DR, AC, IR, TR, OUTR = 7. Clear signals: AC, E, SC = 3. Increment: PC, AC, DR, AR = 4. Bus select: S₂, S₁, S₀ = 3. Memory: Read, Write = 2. ALU: AND, ADD, complement, shift = 4. IEN: set, clear = 2. Misc: INP, OUT = 2. Total ≈ 27+ control signals.

How many clock cycles does each instruction type take (including fetch)? Calculate the total cycles for a program: LDA, ADD, ADD, STA, HLT.

ApplyIntermediate

Fetch = 3 cycles (T₀–T₂). LDA: 3+3 = 6 cycles. ADD: 3+3 = 6 cycles. STA: 3+1 = 4 cycles (T₄ only). HLT: 3+1 = 4 cycles (register-ref, T₃ only). Total: 6+6+6+4+4 = 26 clock cycles. Note: indirect adds 1 extra cycle (T₃).

Industry Application Questions (3)

ARM Cortex-M0 (used in Indian smart meters): The ARM Cortex-M0 has a 3-stage pipeline (Fetch-Decode-Execute). Compare this with Mano's sequential instruction cycle. How does pipelining improve throughput? What hazards can occur?

AnalyzeAdvanced

Mano's computer: one instruction at a time. ARM pipeline: while Instruction 1 executes, Instruction 2 decodes, and Instruction 3 fetches — 3× throughput improvement (ideally). Hazards: Data hazard (instruction needs result of previous), Control hazard (branch changes PC, invalidating prefetched instructions), Structural hazard (two stages need same resource). Indian smart meters by EESL use Cortex-M0 for billing calculations.

ISRO's onboard computers: ISRO's satellite processors need radiation-hardened designs. Why might ISRO prefer a simpler architecture (like Mano's basic computer scaled up) over complex modern CPUs for space applications?

EvaluateAdvanced

Simpler architectures are more reliable: fewer transistors = fewer points of failure. Radiation can flip bits; simpler logic is easier to protect with redundancy (Triple Modular Redundancy). Hardwired control is preferred over microprogrammed (fewer memory elements that can be corrupted). ISRO's SPARC-based processors in Chandrayaan-3 use a RISC architecture with hardwired control — conceptually similar to Mano's approach but scaled up.

Intel microcode updates: In 2018, Intel released microcode patches for the Spectre/Meltdown vulnerabilities. Explain how this was possible using the microprogrammed control concept. Could this be done if Intel used purely hardwired control?

EvaluateAdvanced

Intel x86 CPUs use microprogrammed control with updateable microcode stored in on-chip ROM that can be patched via BIOS/OS updates. The microcode update changed how speculative execution branches are handled. With purely hardwired control, this would be IMPOSSIBLE — the only fix would be a physical chip replacement (recall millions of CPUs!). This is the strongest argument for microprogrammed control in complex processors.

GATE-Style Questions (5)

GATE CSE In Mano's basic computer, the instruction at address 010 (hex) is 0xF400. What operation is performed?

Store AC to memory at address 400
Output AC(0–7) to OUTR
Branch to address 400 unconditionally
Input character from INPR to AC

RememberGATE 2-mark

✅ Answer: (B). 0xF400 = 1111 0100 0000 0000. I=1, Opcode=111, so this is an I/O instruction. Bit 10 = 1 → OUT instruction. OUT transfers AC(0–7) to the output register OUTR.

GATE CSE The common bus system of Mano's basic computer uses a multiplexer with selection lines S₂S₁S₀ = 100. Which register is placed on the bus?

RememberGATE 1-mark

✅ Answer: (C) AC. Encoding: 001=AR, 010=PC, 011=DR, 100=AC, 101=IR, 110=TR, 111=Memory.

GATE CSE During the interrupt cycle of Mano's basic computer, the return address is stored at memory location:

0
1
The address specified in the current instruction
The stack pointer location

UnderstandGATE 1-mark

✅ Answer: (A) 0. During the interrupt cycle, M[0] ← PC (return address stored at address 0). The ISR entry point is at address 1. There is no stack in Mano's basic computer.

GATE CSE How many timing signals are needed to execute the BSA instruction (direct addressing) after fetch-decode?

ApplyGATE 2-mark

✅ Answer: (B) 2. BSA uses T₄ and T₅. T₄: M[AR]←PC, AR←AR+1. T₅: PC←AR, SC←0. Fetch-decode takes T₀–T₂ (3 signals), but the question asks only about execution after decode.

GATE CSE In a microprogrammed control unit, if the control memory has 128 words and each word is 20 bits, what is the total size of the control memory in bits?

2560 bits
2048 bits
1280 bits
5120 bits

ApplyGATE 1-mark

✅ Answer: (A) 2560 bits. 128 words × 20 bits/word = 2560 bits. Control memory size = number of micro-instructions × micro-instruction word length.

Section F

MCQ Assessment Bank — 30 Questions (Bloom's Mapped)

Remember / Identify (Q1–Q6)

The bit-width of the Program Counter (PC) in Mano's Basic Computer is:

8 bits
12 bits
16 bits
32 bits

Remember

✅ Answer: (B) 12 bits — PC holds memory addresses, and the address space is 2¹² = 4096 words.

The opcode for the LDA instruction in Mano's Basic Computer is:

Remember

✅ Answer: (C) 010 — LDA (Load to Accumulator) has opcode 2 (010 in binary).

How many memory-reference instructions are in Mano's Basic Computer?

Remember

✅ Answer: (C) 7 — AND, ADD, LDA, STA, BUN, BSA, ISZ (opcodes 000 to 110).

The Accumulator (AC) in Mano's Basic Computer is:

8 bits wide
12 bits wide
16 bits wide
32 bits wide

Remember

✅ Answer: (C) 16 bits — AC matches the word size of the computer (16 bits).

The I-bit in Mano's instruction format indicates:

Interrupt enable
Immediate operand
Indirect addressing
Input flag

Remember

✅ Answer: (C) Indirect addressing — When I=1 and opcode ≠ 111, the address field points to a location containing the effective address.

Which register holds the instruction currently being executed?

Remember

✅ Answer: (C) IR (Instruction Register) — It holds the 16-bit instruction fetched from memory during T₁.

Understand / Explain (Q7–Q12)

Why is the common bus system preferred over point-to-point connections between registers?

It is faster
It reduces wiring complexity
It allows multiple simultaneous transfers
It increases register count

Understand

✅ Answer: (B) — A common bus needs only n connections for n registers (through MUX), while point-to-point needs n(n-1)/2. Trade-off: only one transfer at a time.

What happens during timing signal T₁ of the instruction cycle?

The opcode is decoded
AR receives PC value
IR receives instruction from memory and PC is incremented
The ALU performs the operation

Understand

✅ Answer: (C) — T₁: IR ← M[AR] (instruction fetch from memory) and PC ← PC + 1 (prepare for next instruction).

Why does the interrupt cycle store the return address at M[0] instead of using a stack?

Stacks hadn't been invented yet
Mano's basic computer has no stack pointer or stack mechanism
M[0] is faster to access
It allows nested interrupts

Understand

✅ Answer: (B) — Mano's basic computer is a minimal design with no stack pointer register. Using M[0] is the simplest approach. This means nested interrupts are NOT supported (IEN is cleared).

Q10

The BSA instruction is used for:

Bit shifting
Block data transfer
Subroutine calls
Bus arbitration

Understand

✅ Answer: (C) — BSA (Branch and Save Address) saves the return address in memory and jumps to the subroutine. It's the equivalent of a CALL instruction in modern processors.

Q11

In hardwired control, what determines the sequence of control signals?

Microcode ROM
Combinational logic gates and timing signals
Software interrupts
Main memory

Understand

✅ Answer: (B) — Hardwired control uses combinational logic that takes decoded opcode bits (D₀–D₇), timing signals (T₀–T₁₅), and condition flags as inputs to produce control signals. No ROM involved.

Q12

What is the purpose of the E (carry) flip-flop?

Enable/disable interrupts
Store the overflow/carry bit from AC operations
Error detection flag
End-of-instruction marker

Understand

✅ Answer: (B) — E stores the carry-out from ADD operations and is used in circular shift operations (CIR, CIL). It extends AC to 17 bits for arithmetic.

Apply / Solve (Q13–Q18)

Q13

If AC = 0x00FF and DR = 0x0F0F, what is the result of AND operation?

0x000F
0x0FFF
0x0F0F
0x00FF

Apply

✅ Answer: (A) 0x000F. 0x00FF = 0000 0000 1111 1111. 0x0F0F = 0000 1111 0000 1111. AND = 0000 0000 0000 1111 = 0x000F.

Q14

S₂S₁S₀ = 011 places which register on the common bus?

Apply

✅ Answer: (C) DR. Encoding: 001=AR, 010=PC, 011=DR, 100=AC, 101=IR, 110=TR, 111=Memory.

Q15

An instruction has hex code 0x7020. What operation does it perform?

INC (increment AC)
CMA (complement AC)
CIR (circular right shift)
ADD

Apply

✅ Answer: (A) INC. 0x7020 = 0111 0000 0010 0000. I=0, Opcode=111 → register-reference. Bit 5 = 1 → INC instruction (increment AC by 1).

Q16

After executing LDA 200 (direct) where M[200] = 0xABCD, what is the value of AC?

0x0200
0xABCD
0x0000
Unchanged

Apply

✅ Answer: (B) 0xABCD. LDA loads the memory word at the effective address into AC. AC ← M[200] = 0xABCD.

Q17

How many words of memory can Mano's Basic Computer address?

256
1024
4096
65536

Apply

✅ Answer: (C) 4096. The address field is 12 bits: 2¹² = 4096 words. Each word is 16 bits, so total memory = 4096 × 16 = 65,536 bits = 8 KB.

Q18

The micro-operation "AR ← IR(0–11)" happens during which timing signal?

T₀
T₁
T₂
T₃

Apply

✅ Answer: (C) T₂. During the decode phase (T₂), the address portion of IR (bits 0–11) is transferred to AR to prepare for operand access.

Analyze / Compare (Q19–Q24)

Q19

Which instruction takes the MOST clock cycles to execute (including fetch) in direct addressing mode?

Analyze

✅ Answer: (C) ISZ — ISZ uses T₄, T₅, T₆ (3 execution cycles) + 3 fetch = 6 total. ADD uses T₄, T₅ (2) + 3 = 5. STA uses T₄ (1) + 3 = 4. BUN uses T₄ (1) + 3 = 4.

Q20

Adding indirect addressing to a memory-reference instruction adds how many extra clock cycles?

Analyze

✅ Answer: (B) 1. At T₃, if I=1: AR ← M[AR] (one memory read to resolve the indirect address). This adds exactly 1 clock cycle.

Q21

Why does Mano's computer use a 3-bit opcode instead of 4-bit?

To save power
To maximize the address field (12 bits) within a 16-bit instruction
Because only 7 instructions exist
Because the ALU is 3 bits wide

Analyze

✅ Answer: (B) — With a 16-bit instruction word, allocating 1 bit for I and 3 bits for opcode leaves 12 bits for the address (4K addressable words). A 4-bit opcode would reduce the address to 11 bits = 2K words.

Q22

In the common bus system, what prevents two registers from driving the bus simultaneously?

Bus arbiter hardware
The MUX allows only one input to pass through at a time
Registers check bus status before writing
The clock signal prevents collisions

Analyze

✅ Answer: (B) — The MUX (multiplexer) physically selects only one input based on S₂S₁S₀. Only the selected register's output reaches the bus. Other register outputs are blocked by the MUX.

Q23

Why is IEN cleared to 0 during the interrupt cycle?

To save power
To prevent nested interrupts
Because the I/O device requested it
To reset the CPU

Analyze

✅ Answer: (B) — Clearing IEN prevents another interrupt from occurring while the current ISR is executing. Mano's basic computer does not support nested interrupts. The ISR must re-enable interrupts with ION before returning.

Q24

What would happen if the sequence counter (SC) is NOT cleared after instruction execution?

The CPU would execute the same instruction twice
Timing signals would continue incrementing, producing incorrect control signals
The bus would be locked
Memory would be corrupted

Analyze

✅ Answer: (B) — If SC is not cleared, it continues to T₇, T₈... which would activate wrong control signals (meant for different instruction phases), causing unpredictable behavior.

Evaluate & Create (Q25–Q30)

Q25

If you could add ONE more register to Mano's Basic Computer, which would improve performance the most?

A second accumulator (AC2)
A stack pointer (SP)
A base register (BR)
A flag register (FR)

Evaluate

✅ Answer: (B) — A stack pointer would enable: (1) nested subroutine calls (currently impossible since BSA overwrites return address), (2) nested interrupts, (3) parameter passing. This is why all real CPUs have a stack pointer.

Q26

Which is a valid criticism of Mano's Basic Computer's bus architecture?

The bus is too wide (16 bits is wasteful)
Only one data transfer can occur per clock cycle, creating a bottleneck
The MUX is unnecessary
Registers should connect directly to memory without a bus

Evaluate

✅ Answer: (B) — The single-bus architecture is a performance bottleneck. Modern CPUs use multiple buses (data bus, address bus, control bus) and even crossbar switches to allow multiple simultaneous transfers.

Q27

A student proposes increasing the opcode field to 5 bits. What is the main disadvantage?

Too many instructions to implement
Address field shrinks to 10 bits = only 1024 addressable words
The I-bit would be eliminated
The clock speed would decrease

Evaluate

✅ Answer: (B) — With 16-bit instructions: 1(I) + 5(opcode) + 10(address) = 16. Address space drops from 4K to 1K words. Trade-off: more instructions but less addressable memory.

Q28

To implement a SUBTRACT instruction in Mano's computer (without adding new hardware), you would:

Use SUB opcode directly
Complement the operand (CMA), increment (INC), then ADD
Use the E flip-flop to borrow
It's impossible without new hardware

Create

✅ Answer: (B) — Subtraction using 2's complement: A - B = A + (~B + 1). Load B into AC, CMA (complement), INC (add 1 = 2's complement), then ADD A. This demonstrates Turing completeness — any operation can be composed from existing ones.

Q29

Design a loop that adds numbers at addresses 100–104 using Mano's instructions. How many instructions are needed (minimum)?

Create

✅ Answer: (C) ~10. You need: CLA (clear AC), ADD 100, ADD 101, ADD 102, ADD 103, ADD 104, STA [result], HLT = 8 for straight-line. With a loop using ISZ: ~10 instructions including counter initialization, indirect addressing, ISZ-based loop control, and BUN. The loop approach is more elegant and scales to any N.

Q30

If you were designing a new instruction "SWAP" that exchanges AC and DR contents, how many timing signals would the execute phase need?

Create

✅ Answer: (C) 3. You need a temporary register: T₁: TR ← AC. T₂: AC ← DR. T₃: DR ← TR. Each transfer requires one bus cycle (only one transfer per clock on a single bus). With a dual-bus, it could be done in 2 cycles.

Section G

Short Answer Questions (8)

SA1

List all 8 registers of Mano's Basic Computer with their bit-widths and primary functions. (4 marks)

Answer: (1) PC [12-bit] — holds address of next instruction. (2) AR [12-bit] — holds memory address for read/write. (3) IR [16-bit] — holds currently fetched instruction. (4) AC [16-bit] — accumulator for ALU operations. (5) DR [16-bit] — holds operand read from memory. (6) TR [16-bit] — temporary storage during instruction execution. (7) INPR [8-bit] — holds input character from keyboard. (8) OUTR [8-bit] — holds output character for display. Additionally, E is a 1-bit carry flip-flop.

SA2

Explain the 16-bit instruction format of Mano's Basic Computer. What is the role of the I-bit? (4 marks)

Answer: The 16-bit format is: Bit 15 = I (addressing mode), Bits 14–12 = Opcode (3 bits, 8 possible operations), Bits 11–0 = Address (12 bits, 4096 locations). The I-bit: When I=0, the address field directly specifies the operand location (direct addressing). When I=1, the address field points to a memory location that contains the actual operand address (indirect addressing). When opcode=111: I=0 means register-reference instruction, I=1 means I/O instruction.

SA3

Write the RTL micro-operations for the fetch phase (T₀, T₁, T₂). Explain what each accomplishes. (5 marks)

Answer: T₀: AR ← PC (transfer PC to AR so memory can be addressed; bus select S₂S₁S₀=010 for PC). T₁: IR ← M[AR], PC ← PC+1 (read instruction from memory into IR; simultaneously increment PC to point to next instruction; bus select S₂S₁S₀=111 for memory). T₂: D₀...D₇ ← Decode IR(14–12), AR ← IR(11–0), I ← IR(15) (decode the opcode using 3×8 decoder producing signals D₀–D₇; load address portion into AR; extract indirect bit). After T₂, the control unit knows which instruction to execute and where the operand is.

SA4

What is the purpose of the sequence counter (SC)? What happens when it is cleared? (3 marks)

Answer: The sequence counter is a 4-bit register that generates timing signals T₀, T₁, T₂... through a 4×16 decoder. It increments by 1 each clock cycle. When SC is cleared (SC ← 0), the timing resets to T₀, starting the fetch phase of the next instruction. SC is cleared at the end of every instruction's execution phase. Without clearing SC, timing signals would continue to T₇, T₈... producing incorrect control signals for subsequent operations.

SA5

How does indirect addressing work in Mano's computer? Give an example with a memory diagram. (4 marks)

Answer: When I=1 and opcode ≠ 111, the address in bits 11–0 doesn't point to the operand directly. Instead, it points to a memory location that contains the actual operand address. Example: Instruction ADD 300 (indirect, I=1). At T₃: AR ← M[AR]. If M[300] = 0x0500, then AR becomes 500. At T₄: DR ← M[500] (the actual operand). Use case: Implementing pointers, array access, and dynamic memory references. The effective address resolution adds one extra clock cycle.

SA6

Differentiate between memory-reference, register-reference, and I/O instructions. How does the CPU distinguish them? (4 marks)

Answer: (1) Memory-reference: opcode = 000–110, uses 12-bit address to access memory. I-bit selects direct/indirect. (2) Register-reference: opcode = 111, I = 0. The 12-bit field has individual operation bits (only one set at a time). Operations affect AC, E, or PC directly without memory access. (3) I/O instructions: opcode = 111, I = 1. The 12-bit field specifies I/O operations (INP, OUT, SKI, SKO, ION, IOF). The CPU distinguishes by first checking if opcode = 111 (D₇ decoder output). If D₇ = 1, check I bit: I=0 → register-reference, I=1 → I/O.

SA7

Explain the interrupt cycle in Mano's Basic Computer. What are T₀, T₁, T₂ micro-operations? (5 marks)

Answer: The interrupt cycle activates after the execute phase when IEN=1 AND (FGI=1 OR FGO=1). T₀: AR ← 0, TR ← PC (save current PC to TR, set AR to address 0). T₁: M[0] ← TR, PC ← 0 (store return address at memory location 0, set PC to 0). T₂: PC ← PC+1, IEN ← 0, SC ← 0 (PC becomes 1 — ISR entry point, disable further interrupts, reset timing). After this, normal fetch begins from address 1, which typically contains a BUN instruction to the actual ISR. IEN is cleared to prevent nested interrupts. The ISR must execute ION to re-enable interrupts before returning via BUN 0 I (indirect jump through M[0]).

SA8

What is the role of the MUX selection lines S₂S₁S₀ in the common bus system? List all encodings. (3 marks)

Answer: S₂S₁S₀ are three control signals from the control unit that determine which register or memory outputs its data onto the 16-bit common bus. Only one source drives the bus per clock cycle. Encodings: 000 = None (bus idle), 001 = AR, 010 = PC, 011 = DR, 100 = AC, 101 = IR, 110 = TR, 111 = Memory M[AR]. The receiving register's Load signal must also be activated simultaneously for the transfer to complete.

Section H

Long Answer Questions (3)

📝 LA1: Complete Micro-operations for All Memory-Reference Instructions (10 marks)

Question: Write the RTL micro-operations for all seven memory-reference instructions (AND, ADD, LDA, STA, BUN, BSA, ISZ) of Mano's Basic Computer. Include the fetch phase, indirect address resolution, and execution phase for each. Clearly label timing signals.

Answer:

Common Fetch Phase (all instructions):
T₀: AR ← PC
T₁: IR ← M[AR], PC ← PC + 1
T₂: AR ← IR(0–11), I ← IR(15), Decode IR(14–12) → D₀–D₇

Indirect Resolution (if I=1 and D₇'=1):
T₃: AR ← M[AR]

AND (D₀): T₄: DR ← M[AR]. T₅: AC ← AC ∧ DR, SC ← 0.
ADD (D₁): T₄: DR ← M[AR]. T₅: AC ← AC + DR, E ← Cout, SC ← 0.
LDA (D₂): T₄: DR ← M[AR]. T₅: AC ← DR, SC ← 0.
STA (D₃): T₄: M[AR] ← AC, SC ← 0.
BUN (D₄): T₄: PC ← AR, SC ← 0.
BSA (D₅): T₄: M[AR] ← PC, AR ← AR + 1. T₅: PC ← AR, SC ← 0.
ISZ (D₆): T₄: DR ← M[AR]. T₅: DR ← DR + 1. T₆: M[AR] ← DR, if(DR=0) PC ← PC+1, SC ← 0.

Key points: STA and BUN are fastest (1 execution cycle). ISZ is slowest (3 execution cycles). BSA is the subroutine mechanism. All clear SC at the end to restart fetch.

📝 LA2: Hardwired vs Microprogrammed Control — Detailed Comparison (10 marks)

Question: Compare hardwired and microprogrammed control unit designs in detail. Draw block diagrams for both, explain their working principles, and analyze trade-offs in speed, flexibility, cost, and design complexity. Give real-world processor examples for each approach.

Answer:

Hardwired Control: Uses combinational logic circuits (AND, OR, NOT gates) to generate control signals. Inputs: decoded opcode bits (D₀–D₇ from 3×8 decoder), timing signals (T₀–T₁₅ from 4×16 decoder driven by sequence counter), I bit, and condition flags (E, AC₁₅, etc.). Output: control signals for register loads, bus select, memory R/W, ALU operations. Speed: Very fast — signals propagate through gates in nanoseconds. Disadvantage: Complex to design for large instruction sets; any change requires hardware redesign.

Microprogrammed Control: Uses a control memory (ROM) storing micro-instructions. Each machine instruction maps to a sequence of micro-instructions via mapping logic. A Control Address Register (CAR) sequences through the ROM. Each micro-instruction word contains bits that directly activate control signals. Speed: Slower due to ROM access time. Advantage: Flexible — changing behavior only requires updating ROM contents. Intel's microcode updates demonstrate this advantage.

Trade-offs: (1) Speed: Hardwired wins. (2) Flexibility: Microprogrammed wins. (3) Design time: Microprogrammed is faster to design. (4) Cost for simple ISA: Hardwired cheaper. (5) Cost for complex ISA: Microprogrammed cheaper (fewer gates). (6) Bug fixing: Microprogrammed allows patches; hardwired requires new chips.

Examples: Hardwired — ARM Cortex (RISC, simple ISA, speed-critical, used in Snapdragon). Microprogrammed — Intel x86 (CISC, complex ISA, needs microcode patches). Mano's Basic Computer uses hardwired control due to its simple 25-instruction ISA.

📝 LA3: I/O Organization and Interrupt Handling (10 marks)

Question: Explain the complete I/O organization of Mano's Basic Computer. Describe the roles of INPR, OUTR, FGI, FGO, and IEN. Explain programmed I/O (polling) vs interrupt-driven I/O. Trace through a complete interrupt cycle with a numerical example.

Answer:

I/O Registers: INPR (8-bit) — receives character from keyboard. OUTR (8-bit) — sends character to display. FGI (1-bit) — set by keyboard when new character ready, cleared by CPU after reading. FGO (1-bit) — set by display when ready for new character, cleared by CPU after writing. IEN (1-bit) — master interrupt enable; 1=interrupts allowed, 0=disabled.

Programmed I/O (Polling): CPU repeatedly checks FGI/FGO in a loop. Example: "Loop: SKI, BUN Loop, INP" — CPU wastes cycles checking if keyboard has input. Simple but extremely inefficient (CPU is idle 99.99% of the time waiting for slow I/O).

Interrupt-Driven I/O: CPU executes main program normally. When I/O device is ready (FGI=1 or FGO=1) AND IEN=1, an interrupt occurs between instruction cycles. CPU saves context, jumps to ISR, handles I/O, returns. Much more efficient.

Example Trace: CPU executing program at PC=500. Keyboard sends 'A' (ASCII 65 = 0x41). FGI ← 1. After current instruction's execute phase: Check IEN=1 AND FGI=1 → YES.
Interrupt Cycle: T₀: AR←0, TR←500. T₁: M[0]←500, PC←0. T₂: PC←1, IEN←0, SC←0.
Now fetch from PC=1: M[1] = BUN 800 (jump to ISR at 800).
ISR at 800: INP (AC(0–7) ← INPR = 0x41), STA 900 (store character), ION (re-enable interrupts), BUN 0 I (indirect: PC ← M[0] = 500, return to main program).

Key: IEN cleared to prevent nested interrupts. ISR must ION before returning.

Section I

Industry Spotlight — A Day in the Life

👨‍💻 Arun Menon, 29 — CPU Design Engineer at ARM India, Bangalore

Background: B.Tech ECE from NIT Calicut. Fascinated by computer organization in 3rd semester. Did an internship at CDAC Thiruvananthapuram working on India's own microprocessor (VEGA RISC-V). Joined ARM India's CPU design team after campus placement.

A Typical Day:

8:30 AM — Sync with the Cambridge (UK) team on the Cortex-X5 core's bus interconnect design. India handles critical modules of ARM's next-gen CPU.

9:30 AM — Run RTL simulations of the load-store unit in Verilog. The bus arbitration logic he designed last week has a timing violation — needs to optimize the critical path.

11:00 AM — Architecture review meeting. Discuss whether to add a second data bus to reduce the bottleneck for memory-intensive workloads (the same bus trade-off from Mano's computer, but at 3 GHz).

1:00 PM — Lunch at ARM's Bangalore campus. Chat about RISC-V's open ISA and India's push for processor sovereignty (SHAKTI project at IIT Madras).

2:00 PM — Write microarchitecture specification for a new "prefetch" instruction. Define the RTL, timing, and control signals — exactly like what you learn with Mano's instructions, but for a real product.

4:00 PM — Debug a gate-level simulation. A register isn't loading at the right timing signal (T₂ instead of T₃). Classic computer organization bug.

5:30 PM — Study session on formal verification methods. ARM encourages continuous learning.

Detail	Info
Tools Used Daily	Verilog/SystemVerilog, Synopsys VCS, ARM Architecture Reference Manual, Python for automation
Entry Salary (2024)	₹12–18 LPA + RSUs
Mid-Level (3–5 yrs)	₹20–35 LPA
Senior (7+ yrs)	₹40–70 LPA
Companies Hiring	ARM, Qualcomm, Samsung R&D, Intel, AMD, NVIDIA, MediaTek, Texas Instruments, Broadcom, ISRO, CDAC, IIT Madras (SHAKTI)
Key Skills	Computer Organization (Mano's + Patterson/Hennessy), Digital Logic, Verilog/VHDL, GATE (for PSU/DRDO path)

Arun's advice to students: "Every concept in Mano's Basic Computer maps to what I do daily at ARM. The bus system, timing signals, control unit — it's the same principles, just scaled up. Master Mano's computer thoroughly, then move to Patterson & Hennessy. If I could give one tip: build a CPU simulator project. It's what got me noticed during my ARM interview."

Section J

Earn With It — CPU Simulator Projects

💰 Your Earning Path After This Chapter

Portfolio Piece: A working CPU simulator (Python or web-based) that implements Mano's Basic Computer with visual register states and step-by-step execution.

Project Ideas That Pay:

• Visual CPU Simulator (HTML/JS) for educational platforms — ₹5,000–₹15,000 per project

• Verilog implementation of Mano's computer for FPGA — ₹10,000–₹25,000 freelance

• YouTube tutorial series on Computer Organization — Ad revenue + course sales

• GATE coaching content creation (COA section) — ₹3,000–₹8,000 per module

Platform	Best For	Typical Rate
Freelancer.com	Verilog/VHDL projects from US/EU universities	$50–$200/project (₹4,000–₹16,000)
Chegg / Course Hero	COA assignment solutions (ethically: tutoring)	$5–$20/answer
Udemy / Skillshare	CPU architecture course creation	₹10,000–₹50,000/month passive
GitHub + Portfolio	Land interviews at ARM/Qualcomm/Intel India	₹12–18 LPA starting salary
GATE Coaching	COA chapter tutoring at local coaching centres	₹500–₹1500/hour

⏱️ Time to First Earning: 3–4 weeks (complete Tier 2 or 3 lab, then list on Freelancer.com or create a YouTube tutorial)

High-Value Project Idea: Build a "Mano's CPU Playground" web app where students can write assembly code, load it into memory, and watch the CPU execute step-by-step with animated bus transfers. Educational tech companies (like Unacademy, PhysicsWallah) pay ₹20,000–₹50,000 for such interactive tools. Email them with a demo link.

Section K

Chapter Summary — Quick Reference

🧠 Key Takeaways

✅ Instruction Format: 16 bits = I(1) + Opcode(3) + Address(12). I=0 direct, I=1 indirect. Opcode 111 → register-ref (I=0) or I/O (I=1).

✅ 8 Registers: PC[12], AR[12], IR[16], AC[16], DR[16], TR[16], INPR[8], OUTR[8]. Plus E (1-bit carry).

✅ Common Bus: 16-bit shared highway. MUX with S₂S₁S₀ selects source. Only ONE register drives bus per cycle.

✅ 25 Instructions: 7 memory-reference + 12 register-reference + 6 I/O.

✅ Fetch-Decode-Execute: T₀: AR←PC. T₁: IR←M[AR], PC++. T₂: Decode opcode, AR←address. T₃+: Execute.

✅ Control Unit: Hardwired (fast, inflexible, RISC) vs Microprogrammed (slower, flexible, CISC).

✅ Memory-Reference: AND/ADD/LDA need T₄–T₅. STA/BUN need T₄ only. BSA needs T₄–T₅. ISZ needs T₄–T₆.

✅ Interrupt: IEN AND (FGI OR FGO) triggers interrupt cycle. Return address at M[0], ISR at address 1. IEN cleared during interrupt.

Essential Formulas & Numbers

Parameter	Value	Why
Word size	16 bits	Instruction and data width
Address space	4096 words (4K)	12-bit address field: 2¹² = 4096
Total memory	4K × 16 bits = 8 KB	4096 words × 16 bits/word
Opcodes	8 (3-bit field)	2³ = 8, of which 7 are memory-ref
Total instructions	25	7 + 12 + 6
MUX inputs	7 + 1 (none)	AR, PC, DR, AC, IR, TR, Memory + idle
Fetch cycles	3 (T₀–T₂)	Same for ALL instructions
Fastest instruction	4 cycles (STA, BUN, register-ref)	3 fetch + 1 execute
Slowest instruction	7 cycles (ISZ indirect)	3 fetch + 1 indirect + 3 execute

Section L

Earning Checkpoint — Are You Ready to Earn?

Skill	Tool/Method	Portfolio Evidence	Earning Ready?
Instruction Format Decoding	Manual / Paper	—	✅ Yes — GATE prep tutoring
Trace Table Execution	Paper / Spreadsheet	Completed trace for all 7 instructions	✅ Yes — COA tutoring at ₹500–₹1500/hr
CPU Simulator (Python)	Python	Working simulator on GitHub	✅ Yes — Freelance projects ₹5K–₹15K
Visual CPU Simulator (Web)	HTML/CSS/JS	Live demo on GitHub Pages	✅ Yes — EdTech projects ₹20K–₹50K
Verilog/VHDL Implementation	Verilog, FPGA	Synthesizable code + simulation waveforms	✅ Yes — ₹10K–₹25K freelance
Control Unit Design	Conceptual + Diagrams	Hardwired vs Micro comparison document	✅ Yes — GATE content creation
Interrupt Handling	Conceptual	—	⬜ Need hands-on with real µController

Minimum Viable Earning Setup after this chapter: A GitHub profile with a working CPU simulator (Python or web-based) + understanding of Mano's architecture = you can tutor GATE COA for ₹500–₹1500/hour, take Verilog freelance projects for ₹5,000–₹25,000, or create educational content for passive income. ARM/Qualcomm India interviews directly test these concepts.

✅ Unit 3 complete. You now understand how a computer is organized from the ground up!

[QR: Link to EduArtha video tutorial — Computer Organization & Mano's Basic Computer]