Computer Organization & Architecture

Unit 2: Register Transfer & Micro Operations

From flip-flop arrays to ALU internals — master register transfers, micro operations, bus systems, and build a working shift-register simulator.

⏱️ 5 hrs theory + 3 hrs lab | 🎯 GATE ~3 marks | 🖥️ Intel Core i9 Registers

Section A

Opening Hook — The Registers Inside Your Processor

🖥️ Intel Core i9 — 32 General-Purpose Registers Running at 6 GHz

Right now, inside your laptop or desktop, the Intel Core i9 processor has 32 general-purpose registers, each 64 bits wide. Every single instruction your computer executes — opening Chrome, playing a video, compiling code — involves data moving between these registers at speeds exceeding 6 billion cycles per second.

When you type a = b + c in C, the compiler translates it into register-level operations: Load b into R1, Load c into R2, ADD R1+R2→R3, Store R3 to memory. These tiny operations — called micro operations — are the atomic building blocks of everything a CPU does.

Understanding register transfers and micro operations is understanding how a processor actually thinks. This chapter teaches you the exact language (RTL — Register Transfer Language) that hardware designers at Intel, AMD, and Qualcomm use to describe what happens inside a chip — one clock pulse at a time.

🖥️ Intel🖥️ AMD🇮🇳 Qualcomm India🇮🇳 Samsung R&D🇮🇳 ARM India🇮🇳 ISRO VSSC

A single Intel Core i9-14900K contains over 2 billion transistors forming registers, ALUs, and data paths. Every register transfer you'll study in this chapter happens physically — flip-flops toggling, buses carrying bits, multiplexers selecting paths — all within a chip smaller than your thumbnail. GATE CSE has asked 2–3 marks on register transfer and micro operations every year since 2018.

Section B

Learning Outcomes — Bloom's Taxonomy Mapped

Bloom's Level	Learning Outcome
🔵 Remember	Define register, register transfer, and list all RTL notation symbols with their meanings
🔵 Remember	State the four types of micro operations: register transfer, arithmetic, logic, and shift
🔵 Understand	Explain how a common bus system uses multiplexers to connect multiple registers to a shared data path
🔵 Understand	Describe memory read and memory write operations using RTL notation (DR←M[AR], M[AR]←DR)
🟢 Apply	Trace the step-by-step execution of conditional register transfers with timing diagrams
🟢 Apply	Perform selective-set, selective-clear, selective-complement, and insert operations on binary data
🟢 Analyze	Compare logical, circular, and arithmetic shift operations and predict the output for any 8-bit input
🟢 Analyze	Differentiate SISO, SIPO, PISO, and PIPO shift registers by data flow and application
🟠 Evaluate	Determine the correct ALSU function-select code (S₃S₂S₁S₀) for a given micro operation
🟠 Evaluate	Justify why bus-based architecture is preferred over direct register-to-register connections in CPU design
🟠 Create	Write a Python simulator for an 8-bit shift register supporting all shift types
🟠 Create	Design a complete ALSU operation table mapping function-select bits to arithmetic, logic, and shift outputs

Section C

Concept Explanation — Register Transfer & Micro Operations from Scratch

1. Register — The CPU's Scratchpad

A register is a group of flip-flops (bistable circuits) that stores binary information. Each flip-flop stores one bit. An n-bit register has n flip-flops and can store any value from 0 to 2ⁿ−1.

Analogy: Think of a register like a row of light switches. Each switch is either ON (1) or OFF (0). A 16-bit register is like 16 switches lined up — together they represent a 16-bit binary number.

📐 16-Bit Register with Parallel Load

  ┌────────────────────────────────────────────────────────────────────┐
  │                    16-BIT PARALLEL LOAD REGISTER                  │
  │                                                                    │
  │  Input:  I₁₅  I₁₄  I₁₃  I₁₂  I₁₁  I₁₀  I₉  I₈  I₇  I₆  I₅  I₄  I₃  I₂  I₁  I₀  │
  │           │    │    │    │    │    │    │   │   │   │   │   │   │   │   │   │   │
  │           ▼    ▼    ▼    ▼    ▼    ▼    ▼   ▼   ▼   ▼   ▼   ▼   ▼   ▼   ▼   ▼   │
  │         ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐┌──┐┌──┐┌──┐┌──┐┌──┐┌──┐┌──┐┌──┐┌──┐│
  │  LOAD──▶│FF│ │FF│ │FF│ │FF│ │FF│ │FF│ │FF││FF││FF││FF││FF││FF││FF││FF││FF││FF││
  │         │15│ │14│ │13│ │12│ │11│ │10│ │ 9││ 8││ 7││ 6││ 5││ 4││ 3││ 2││ 1││ 0││
  │         └──┘ └──┘ └──┘ └──┘ └──┘ └──┘ └──┘└──┘└──┘└──┘└──┘└──┘└──┘└──┘└──┘└──┘│
  │  CLK──────────────────────────────────────────────────────────────────────────────│
  │           │    │    │    │    │    │    │   │   │   │   │   │   │   │   │   │   │
  │           ▼    ▼    ▼    ▼    ▼    ▼    ▼   ▼   ▼   ▼   ▼   ▼   ▼   ▼   ▼   ▼   │
  │  Output: Q₁₅  Q₁₄  Q₁₃  Q₁₂  Q₁₁  Q₁₀  Q₉  Q₈  Q₇  Q₆  Q₅  Q₄  Q₃  Q₂  Q₁  Q₀  │
  └────────────────────────────────────────────────────────────────────┘

  Key Signals:
  • LOAD = 1 → On next CLK edge, inputs (I₁₅...I₀) are loaded into register
  • LOAD = 0 → Register retains its current value (no change)
  • CLK      → All flip-flops are triggered simultaneously (parallel load)

How it works: When LOAD = 1, on the rising edge of CLK, all 16 input bits are simultaneously captured by the 16 flip-flops. When LOAD = 0, the register holds its previous value — this is the "memory" property. The outputs Q₁₅…Q₀ always reflect the currently stored value.

GATE Tip: A register is NOT just storage — it has a clock input (synchronization), a load control (when to store), and parallel outputs. Questions often test whether you understand that without LOAD = 1, the register does not change even if inputs change.

2. Register Transfer — Moving Data Between Registers

A register transfer operation copies the contents of one register into another. It is the most fundamental operation inside a CPU.

📐 Register Transfer: R2 ← R1

  ┌───────────┐                         ┌───────────┐
  │           │    n-bit data bus        │           │
  │    R1     │ ═══════════════════════▶ │    R2     │
  │ (Source)  │    Q₁₅...Q₀ of R1       │  (Dest)   │
  │           │                         │           │
  └─────┬─────┘                         └─────┬─────┘
        │                                     │
        │   ┌─────────────────────────┐       │
        └───│      CLK (shared)       │───────┘
            └─────────────────────────┘

  RTL Statement:  R2 ← R1

  Meaning: Copy the contents of R1 into R2.
  R1 is NOT modified (source is read, not erased).
  Transfer happens on the clock edge.

Conditional Register Transfer

         ┌─────┐
  P ────▶│ AND │──── LOAD input of R2
  CLK ──▶│     │
         └─────┘

  RTL Statement:  P: R2 ← R1

  Meaning: IF control signal P = 1,
           THEN on the next clock edge, R2 gets the value of R1.
           IF P = 0, R2 remains unchanged.

  Timing Diagram:
  CLK:    ─┐  ┌──┐  ┌──┐  ┌──┐  ┌──
           └──┘  └──┘  └──┘  └──┘
  P:      ─────┐           ┌──────────
               └───────────┘
  R2:     [old] [old] [R1]  [R1] [R1]
                      ▲
                      Transfer occurs here (P=1 at CLK edge)

R2 ← R1 does NOT erase R1. This is a copy, not a move. After the transfer, both R1 and R2 hold the same value. Students in GATE often assume R1 becomes zero — it doesn't.

3. RTL (Register Transfer Language) Notation

RTL is a symbolic notation to describe micro operations precisely. It's the "assembly language" of hardware design.

RTL Notation Rules

Rule	Description	Example
Registers	Denoted by uppercase letters with optional numbers	`R1, R2, AR, DR, AC, PC`
Arrow ←	Denotes transfer (destination ← source)	`R2 ← R1`
Comma ,	Separates simultaneous operations	`R1 ← R2, R3 ← R4`
Colon :	Separates condition from operation	`P: R2 ← R1`
Parentheses ()	Denote specific bits of a register	`R1(0-7)` = lower 8 bits
Brackets []	Denote memory word address	`M[AR]` = memory at address AR

RTL Operation Examples

#	RTL Statement	Meaning	Type
1	`R2 ← R1`	Copy R1 into R2	Transfer
2	`P: R2 ← R1`	If P=1, copy R1 into R2	Conditional Transfer
3	`R1 ← R1 + R2`	Add R1 and R2, store in R1	Arithmetic
4	`R3 ← R1 + R̄2 + 1`	Subtract: R3 ← R1 − R2 (2's complement)	Arithmetic
5	`R1 ← R1 ∧ R2`	Bitwise AND of R1 and R2	Logic
6	`R1 ← R1 ∨ R2`	Bitwise OR of R1 and R2	Logic
7	`R1 ← R1 ⊕ R2`	Bitwise XOR of R1 and R2	Logic
8	`R1 ← R̄1`	Complement (NOT) all bits of R1	Logic
9	`R1 ← shl R1`	Shift R1 left by 1 bit	Shift
10	`R1 ← shr R1`	Shift R1 right by 1 bit	Shift
11	`DR ← M[AR]`	Memory read: load memory word at address AR into DR	Memory
12	`M[AR] ← DR`	Memory write: store DR into memory at address AR	Memory
13	`R1 ← R2, R3 ← R4`	Simultaneous: copy R2→R1 AND R4→R3 in same clock	Parallel Transfer

4. Bus & Memory Transfer — The Shared Highway

Problem: If you have 8 registers and each can transfer to any other, you need 8×7 = 56 direct connections. That's a wiring nightmare!

Solution: Use a common bus — a shared set of wires that any register can place data on, and any register can read from, but only one at a time.

Bus = Mumbai Local Train — shared track, one train at a time. Just like Mumbai's local railway has a shared track where only one train can occupy a section at a time, the common bus is a shared data path. Only one register can "drive" (place data on) the bus at a time, while any other register can "listen" (read from) the bus. Traffic management is handled by MUX select lines, just like railway signals manage train scheduling.

📐 Common Bus System — 3 Registers + ALU via MUX

       R1 (n bits)       R2 (n bits)       R3 (n bits)
      ┌──────────┐      ┌──────────┐      ┌──────────┐
      │          │      │          │      │          │
      │  Q₁...Qₙ │      │  Q₁...Qₙ │      │  Q₁...Qₙ │
      └────┬─────┘      └────┬─────┘      └────┬─────┘
           │                  │                  │
           │    ┌─────────────┼──────────────────┘
           │    │             │
           ▼    ▼             ▼
      ┌────────────────────────────┐
      │     n-bit MUX (n:1)       │
      │                            │
      │   S₁ S₀ (select lines)    │     S₁S₀ = 00 → R1 on bus
      │   ─┬──┬─                  │     S₁S₀ = 01 → R2 on bus
      │    │  │                    │     S₁S₀ = 10 → R3 on bus
      └────┼──┼────────────────────┘
           │  │         │
           │  │         ▼
           │  │  ════════════════════  ← COMMON BUS (n bits wide)
           │  │         │
           │  │    ┌────┴────┐
           │  │    │         │
           ▼  ▼    ▼         ▼
      ┌──────────┐    ┌──────────┐
      │   ALU    │    │ Any Reg  │
      │          │    │ (LOAD=1) │
      └──────────┘    └──────────┘

  Operation Example:  R3 ← R1 + R2
  Step 1: S₁S₀ = 00 → R1 placed on bus → ALU input A
  Step 2: S₁S₀ = 01 → R2 placed on bus → ALU input B
  Step 3: ALU performs ADD → result placed on bus
  Step 4: R3 LOAD = 1 → R3 captures result from bus on CLK edge

Memory Read & Write Operations

📐 Memory Transfer Operations

  MEMORY READ:  DR ← M[AR]
  ──────────────────────────────────────────────────────
    ┌──────────┐         ┌───────────────────┐
    │   AR     │────────▶│    MEMORY         │
    │ (Address │  addr   │                   │
    │ Register)│  bus    │  Address Decoder   │
    └──────────┘         │        │          │
                         │   ┌────▼────┐     │
                         │   │ Cell at │     │
    ┌──────────┐         │   │ AR addr │     │
    │   DR     │◀────────│   └────┬────┘     │
    │  (Data   │  data   │        │          │
    │ Register)│  bus    │   data out        │
    └──────────┘         └───────────────────┘

    Control: READ = 1
    Result:  DR gets the word stored at memory address AR

  MEMORY WRITE:  M[AR] ← DR
  ──────────────────────────────────────────────────────
    ┌──────────┐         ┌───────────────────┐
    │   AR     │────────▶│    MEMORY         │
    │ (Address │  addr   │                   │
    │ Register)│  bus    │  Address Decoder   │
    └──────────┘         │        │          │
                         │   ┌────▼────┐     │
    ┌──────────┐         │   │ Cell at │     │
    │   DR     │────────▶│   │ AR addr │     │
    │  (Data   │  data   │   └─────────┘     │
    │ Register)│  bus    │                   │
    └──────────┘         └───────────────────┘

    Control: WRITE = 1
    Result:  The word in DR is written into memory at address AR

AR always holds the address, DR always holds the data. In memory read, data flows FROM memory TO DR. In memory write, data flows FROM DR TO memory. The direction of the arrow in RTL tells you the direction of data flow: destination ← source.

5. Logic Micro Operations

Logic micro operations perform bit-by-bit (bitwise) operations on data stored in registers. These do NOT consider carry or sign — each bit is processed independently.

Truth Tables for Basic Logic Operations

A	B	A ∧ B (AND)	A ∨ B (OR)	A ⊕ B (XOR)	Ā (Complement)
0	0	0	0	0	1
0	1	0	1	1	1
1	0	0	1	1	0
1	1	1	1	0	0

Selective Operations — Practical Applications

📐 Selective Set, Clear, Complement & Insert

Selective Set (using OR)

Set specific bits to 1 without disturbing others. OR with a mask where 1 = set that bit.

  R1 =     1 0 1 0  0 1 1 0     (original)
  Mask =   0 0 0 0  1 1 0 0     (set bits 2,3)
  ─────────────────────────────
  R1∨Mask= 1 0 1 0  1 1 1 0     (bits 2,3 are now 1, others unchanged)

  RTL: R1 ← R1 ∨ B     (B is the mask register)

Selective Clear (using AND with complement)

Clear specific bits to 0 without disturbing others. AND with complement of mask.

  R1 =      1 0 1 0  1 1 1 0     (original)
  Mask =    0 0 0 0  1 1 0 0     (clear bits 2,3)
  B̄ =       1 1 1 1  0 0 1 1     (complement of mask)
  ─────────────────────────────────
  R1 ∧ B̄ =  1 0 1 0  0 0 1 0     (bits 2,3 are now 0, others unchanged)

  RTL: R1 ← R1 ∧ B̄

Selective Complement (using XOR)

Toggle specific bits. XOR with a mask where 1 = toggle that bit.

  R1 =      1 0 1 0  1 1 1 0     (original)
  Mask =    0 0 0 0  1 1 0 0     (toggle bits 2,3)
  ─────────────────────────────────
  R1⊕Mask = 1 0 1 0  0 0 1 0     (bits 2,3 are toggled, others unchanged)

  RTL: R1 ← R1 ⊕ B

Insert Operation (Clear then Set)

Replace specific bits with new values. First CLEAR the target bits, then OR with new values.

  R1 =        1 0 1 0  1 1 1 0     (original — want to insert 01 at bits 2,3)
  Step 1 — Clear bits 2,3:
    Mask =    0 0 0 0  1 1 0 0
    B̄ =       1 1 1 1  0 0 1 1
    R1∧B̄ =    1 0 1 0  0 0 1 0     (bits 2,3 cleared)

  Step 2 — Insert new value 01 at bits 2,3:
    New =     0 0 0 0  0 1 0 0     (01 positioned at bits 2,3)
    Result =  1 0 1 0  0 1 1 0     (bits 2,3 = 01, others unchanged)

  RTL: R1 ← (R1 ∧ B̄) ∨ New

Logic micro operations are the backbone of bit manipulation in embedded systems. When ISRO engineers program the Chandrayaan-3 telemetry system, they use selective set/clear operations to pack multiple sensor readings into a single 32-bit register — saving precious bandwidth on the deep-space communication link.

6. Shift Register Types — SISO, SIPO, PISO, PIPO

A shift register is a group of flip-flops connected in a chain, where each flip-flop passes its output to the next on every clock pulse. The type depends on how data enters and exits:

Type	Full Name	Input	Output	Application
SISO	Serial In Serial Out	1 bit at a time	1 bit at a time	Delay lines, time delay
SIPO	Serial In Parallel Out	1 bit at a time	All bits together	Serial-to-parallel conversion
PISO	Parallel In Serial Out	All bits together	1 bit at a time	Parallel-to-serial conversion
PIPO	Parallel In Parallel Out	All bits together	All bits together	Buffer register, temporary storage

📐 4-Bit Shift Register Types — ASCII Diagrams

SISO — Serial In, Serial Out

  Data In (1 bit) ──▶ ┌────┐   ┌────┐   ┌────┐   ┌────┐ ──▶ Data Out (1 bit)
                      │ FF₃ │──▶│ FF₂ │──▶│ FF₁ │──▶│ FF₀ │
               CLK ──▶└────┘   └────┘   └────┘   └────┘
                      
  Data flow: Input → FF₃ → FF₂ → FF₁ → FF₀ → Output
  Takes 4 clock cycles to load/read 4 bits.

  Example: Input sequence 1,0,1,1 (one bit per clock)
  CLK 1:  [1] [0] [0] [0]   ← 1 enters FF₃
  CLK 2:  [0] [1] [0] [0]   ← 0 enters, 1 shifts right
  CLK 3:  [1] [0] [1] [0]   ← 1 enters, others shift
  CLK 4:  [1] [1] [0] [1]   ← 1 enters, first bit exits FF₀

SIPO — Serial In, Parallel Out

  Data In (1 bit) ──▶ ┌────┐   ┌────┐   ┌────┐   ┌────┐
                      │ FF₃ │──▶│ FF₂ │──▶│ FF₁ │──▶│ FF₀ │
               CLK ──▶└──┬─┘   └──┬─┘   └──┬─┘   └──┬─┘
                         │        │        │        │
                         ▼        ▼        ▼        ▼
                        Q₃       Q₂       Q₁       Q₀   (Parallel Output)

  Usage: Convert serial data (UART) to parallel (CPU bus)

PISO — Parallel In, Serial Out

  D₃       D₂       D₁       D₀      (Parallel Input)
   │        │        │        │
   ▼        ▼        ▼        ▼
  ┌────┐   ┌────┐   ┌────┐   ┌────┐ ──▶ Data Out (1 bit)
  │ FF₃ │──▶│ FF₂ │──▶│ FF₁ │──▶│ FF₀ │
  └────┘   └────┘   └────┘   └────┘
  LOAD/SHIFT ──────────────────────┘

  Mode 1 (LOAD=1): All 4 bits loaded simultaneously
  Mode 2 (SHIFT=1): Bits shift right, one exits per clock
  Usage: Convert parallel data (CPU bus) to serial (USB/UART)

PIPO — Parallel In, Parallel Out

  D₃       D₂       D₁       D₀      (Parallel Input)
   │        │        │        │
   ▼        ▼        ▼        ▼
  ┌────┐   ┌────┐   ┌────┐   ┌────┐
  │ FF₃ │   │ FF₂ │   │ FF₁ │   │ FF₀ │
  └──┬─┘   └──┬─┘   └──┬─┘   └──┬─┘
     │        │        │        │
     ▼        ▼        ▼        ▼
    Q₃       Q₂       Q₁       Q₀   (Parallel Output)
  
  LOAD ───────────────────────────┘

  Usage: Buffer/temporary register, pipeline stage

7. Shift Micro Operations

Shift micro operations move bits within a register left or right. There are three types:

Shift Type	Direction	What Happens	Vacated Bit	Use Case
Logical Shift Left	←	All bits move left by 1	LSB = 0	Multiply by 2
Logical Shift Right	→	All bits move right by 1	MSB = 0	Unsigned divide by 2
Circular Shift Left	← (rotate)	All bits rotate left	LSB = old MSB	Cryptography, CRC
Circular Shift Right	→ (rotate)	All bits rotate right	MSB = old LSB	Bit pattern rotation
Arithmetic Shift Right	→	All bits move right	MSB = old MSB (sign preserved)	Signed divide by 2

8-Bit Shift Trace Table

📐 Before/After Trace — All 5 Shift Types on 10110011

Operation	Before (8 bits)	After (8 bits)	Notes
Logical Shift Left	`1 0 1 1 0 0 1 1`	`0 1 1 0 0 1 1 0`	MSB (1) lost, LSB = 0
Logical Shift Right	`1 0 1 1 0 0 1 1`	`0 1 0 1 1 0 0 1`	LSB (1) lost, MSB = 0
Circular Shift Left	`1 0 1 1 0 0 1 1`	`0 1 1 0 0 1 1 1`	MSB (1) wraps to LSB
Circular Shift Right	`1 0 1 1 0 0 1 1`	`1 1 0 1 1 0 0 1`	LSB (1) wraps to MSB
Arithmetic Shift Right	`1 0 1 1 0 0 1 1`	`1 1 0 1 1 0 0 1`	MSB (sign=1) preserved, LSB lost

  Logical Shift Left:    [1 0 1 1 0 0 1 1]  →  ←shift←  →  [0 1 1 0 0 1 1 0]
                          ↑ lost                                           ↑ zero fill
  
  Logical Shift Right:   [1 0 1 1 0 0 1 1]  →  →shift→  →  [0 1 0 1 1 0 0 1]
                     zero fill ↑                                           ↑ lost
  
  Circular Shift Left:   [1 0 1 1 0 0 1 1]  →  ←rotate← →  [0 1 1 0 0 1 1 1]
                          ↑───────wraps around──────────────────────────────↑
  
  Circular Shift Right:  [1 0 1 1 0 0 1 1]  →  →rotate→ →  [1 1 0 1 1 0 0 1]
                          ↑──────────────────────────────wraps around──────↑
  
  Arithmetic Shift Right:[1 0 1 1 0 0 1 1]  →  →shift→  →  [1 1 0 1 1 0 0 1]
                     sign bit preserved ↑                                  ↑ lost

Arithmetic Shift Right ≠ Logical Shift Right for negative numbers. For the value 10110011 (−77 in signed 8-bit), logical shift right gives 01011001 (+89, wrong!), while arithmetic shift right gives 11011001 (−39, correctly halved). GATE loves testing this distinction.

8. Arithmetic Logic Shift Unit (ALSU) — Complete Block Diagram

The ALSU (Arithmetic Logic Shift Unit) is the central processing component of any CPU. It combines three sub-units — arithmetic, logic, and shift — controlled by function-select lines.

📐 ALSU Complete Block Diagram

                           A (n bits)              B (n bits)
                             │                       │
                ┌────────────┼───────────────────────┼────────────┐
                │            │                       │            │
                │     ┌──────┴──────┐         ┌──────┴──────┐     │
                │     │             │         │             │     │
                │     ▼             ▼         ▼             ▼     │
                │  ┌────────────────────┐  ┌────────────────┐     │
                │  │   ARITHMETIC UNIT  │  │   LOGIC UNIT   │     │
                │  │                    │  │                │     │
                │  │  Operations:       │  │  Operations:   │     │
                │  │  • Add (A + B)     │  │  • A ∧ B (AND) │     │
                │  │  • Subtract        │  │  • A ∨ B (OR)  │     │
                │  │    (A + B̄ + 1)     │  │  • A ⊕ B (XOR) │     │
                │  │  • Increment (A+1) │  │  • Ā (NOT)     │     │
                │  │  • Decrement (A−1) │  │                │     │
                │  │  • Transfer (A)    │  │                │     │
                │  └────────┬───────────┘  └───────┬────────┘     │
                │           │                      │              │
                │           ▼                      ▼              │
                │  ┌─────────────────────────────────────────┐    │
                │  │              4×1 MUX                     │    │
                │  │                                          │    │
                │  │   Inputs: Arith | Logic | Shift | (rsv)  │    │
                │  │                                          │    │
                │  │         S₃ S₂  (Unit Select)             │    │
                │  │         ─┬──┬─                           │    │
                │  └──────────┼──┼────────────────────────────┘    │
                │             │  │          │                      │
                │      ┌──────┴──┴──────┐   │                      │
                │      │                │   │                      │
                │      ▼                │   │                      │
                │  ┌────────────────┐   │   │                      │
  A (n bits) ──────▶  SHIFT UNIT    │   │   │                      │
                │  │                │   │   │                      │
                │  │  Operations:   │   │   │                      │
                │  │  • Shift Left  │───┘   │                      │
                │  │  • Shift Right │       │                      │
                │  │  • Rotate L/R  │       │                      │
                │  │  • Arith Shr   │       │                      │
                │  └────────────────┘       │                      │
                │                           │                      │
                │                           ▼                      │
                │                    ┌──────────────┐              │
                │                    │   OUTPUT F   │              │
                │                    │   (n bits)   │              │
                │                    └──────────────┘              │
                │                                                  │
                │    S₃S₂ = Unit Select    S₁S₀ = Op Select       │
                │    ──────────────────    ──────────────          │
                │    00 = Arithmetic       Selects which           │
                │    01 = Logic            operation within        │
                │    10 = Shift            the selected unit       │
                │    11 = Reserved                                 │
                │                                                  │
                └──────────────────────────────────────────────────┘

                 Function Select Lines: S₃ S₂ S₁ S₀  +  Cᵢₙ (carry in)

ALSU Operation Table

S₃	S₂	S₁	S₀	Cᵢₙ	Operation	Function	Type
0	0	0	0	0	F = A	Transfer A	Arithmetic
0	0	0	0	1	F = A + 1	Increment A	Arithmetic
0	0	0	1	0	F = A + B	Addition	Arithmetic
0	0	0	1	1	F = A + B + 1	Add with carry	Arithmetic
0	0	1	0	0	F = A + B̄	A plus 1's comp B	Arithmetic
0	0	1	0	1	F = A + B̄ + 1	Subtraction (A − B)	Arithmetic
0	0	1	1	0	F = A − 1	Decrement A	Arithmetic
0	0	1	1	1	F = A	Transfer A	Arithmetic
0	1	0	0	×	F = A ∧ B	AND	Logic
0	1	0	1	×	F = A ∨ B	OR	Logic
0	1	1	0	×	F = A ⊕ B	XOR	Logic
0	1	1	1	×	F = Ā	Complement A	Logic
1	0	0	0	×	F = shl A	Logical Shift Left	Shift
1	0	0	1	×	F = shr A	Logical Shift Right	Shift
1	0	1	0	×	F = cil A	Circular Shift Left	Shift
1	0	1	1	×	F = cir A	Circular Shift Right	Shift

GATE Shortcut: S₃S₂ selects the unit (00=Arith, 01=Logic, 10=Shift). S₁S₀ selects the operation within that unit. For arithmetic operations, Cᵢₙ adds +1. Remembering this 2-level selection makes the entire table easy to reconstruct during the exam.

Section D

Learn by Doing — 3-Tier Lab Structure

🟢 Tier 1 — GUIDED: RTL Trace Exercise

⏱️ 30–45 minutesBeginnerPen-and-paper trace

Problem: Trace the following RTL sequence

Given initial values: R1 = 1010 0110, R2 = 0011 1100, R3 = 0000 0000. Trace each step:

  Step 1:  R3 ← R1          (Transfer)
  Step 2:  R1 ← R1 ∧ R2     (AND)
  Step 3:  R2 ← R2 ∨ R3     (OR)
  Step 4:  R3 ← R1 ⊕ R2     (XOR)

Solution Trace:

Step	Operation	R1	R2	R3
Initial	—	`1010 0110`	`0011 1100`	`0000 0000`
1	R3 ← R1	`1010 0110`	`0011 1100`	`1010 0110`
2	R1 ← R1 ∧ R2	`0010 0100`	`0011 1100`	`1010 0110`
3	R2 ← R2 ∨ R3	`0010 0100`	`1011 1110`	`1010 0110`
4	R3 ← R1 ⊕ R2	`0010 0100`	`1011 1110`	`1001 1010`

Your Turn: Now trace with R1 = 1111 0000, R2 = 0000 1111, and the same 4 steps. Verify your answer by checking: after Step 2, R1 should be all zeros.

🟡 Tier 2 — SEMI-GUIDED: Shift Operations Drill

⏱️ 45–60 minutesIntermediateAll 5 shift types

Exercise: Complete the shift table

Given the 8-bit value: 11001010 (decimal −54 signed, 202 unsigned)

Operation	Input	Your Answer	Decimal (unsigned)
Logical Shift Left ×1	`11001010`	`10010100`	148
Logical Shift Right ×1	`11001010`	`01100101`	101
Logical Shift Left ×2	`11001010`	`00101000`	40
Circular Shift Left ×1	`11001010`	`10010101`	149
Circular Shift Right ×1	`11001010`	`01100101`	101
Arithmetic Shift Right ×1	`11001010`	`11100101`	−27 (signed)
Arithmetic Shift Right ×2	`11001010`	`11110010`	−14 (signed)

Quick Check: Logical shift left = multiply by 2 (unsigned). Arithmetic shift right = divide by 2 (signed, rounds toward −∞). If the value is 11001010 (−54 signed), one arithmetic right shift gives 11100101 (−27). Two gives 11110010 (−14). The sign bit ALWAYS stays.

🔴 Tier 3 — OPEN CHALLENGE: Python 8-Bit Shift Register Simulator

⏱️ 90–120 minutesAdvancedBuild a working simulator

Your Mission: Build a Complete Shift Register Simulator in Python

Create a program that simulates an 8-bit register with all micro operations.

Python
class ShiftRegister:
    def __init__(self, value=0):
        # Store as 8-bit integer (0-255)
        self.value = value & 0xFF
        self.size = 8

    def display(self):
        binary = format(self.value, '08b')
        print(f"  Register: [{binary}]  (Dec: {self.value}, Hex: 0x{self.value:02X})")

    def logical_shift_left(self):
        # All bits shift left, LSB = 0, MSB is lost
        self.value = (self.value << 1) & 0xFF

    def logical_shift_right(self):
        # All bits shift right, MSB = 0, LSB is lost
        self.value = (self.value >> 1) & 0x7F

    def circular_shift_left(self):
        # MSB wraps to LSB
        msb = (self.value >> 7) & 1
        self.value = ((self.value << 1) | msb) & 0xFF

    def circular_shift_right(self):
        # LSB wraps to MSB
        lsb = self.value & 1
        self.value = ((self.value >> 1) | (lsb << 7)) & 0xFF

    def arithmetic_shift_right(self):
        # Sign bit preserved, LSB is lost
        sign = self.value & 0x80
        self.value = ((self.value >> 1) | sign) & 0xFF

# === Test the simulator ===
reg = ShiftRegister(0b10110011)
print("Original:")
reg.display()

reg.logical_shift_left()
print("After Logical Shift Left:")
reg.display()

Original: Register: [10110011] (Dec: 179, Hex: 0xB3) After Logical Shift Left: Register: [01100110] (Dec: 102, Hex: 0x66)

Extension Challenges:
• Add AND, OR, XOR operations with a second register
• Implement the selective set/clear/complement/insert operations
• Build an interactive menu that lets users choose operations
• Add ALSU function-select: user enters S₃S₂S₁S₀ and Cᵢₙ → output result

Section E

Problem Bank — Diagram, Numerical, Industry & GATE

📐 Diagram-Based Problems (3)

Draw a 4-bit common bus system using 4×1 MUX connecting four registers R0, R1, R2, R3. Label select lines S₁S₀ and show which register is placed on bus for each select combination.

  R0    R1    R2    R3
  │     │     │     │
  └──┬──┘  ┌──┘     │
     │     │        │
     ▼     ▼        ▼
  ┌──────────────────────┐
  │     4×1 MUX          │
  │  S₁S₀ = 00 → R0     │
  │  S₁S₀ = 01 → R1     │
  │  S₁S₀ = 10 → R2     │
  │  S₁S₀ = 11 → R3     │
  └──────────┬───────────┘
             │
        COMMON BUS

Each MUX is n-bits wide (one MUX per bit position). For n-bit registers, we need n separate 4×1 MUX circuits.

Draw the block diagram of a 4-bit SIPO shift register. Show the serial input, all 4 flip-flops, clock, and parallel outputs Q₃Q₂Q₁Q₀. Trace the loading of the value 1011 over 4 clock cycles.

  Serial In → [FF₃] → [FF₂] → [FF₁] → [FF₀]
                ↓        ↓        ↓        ↓
               Q₃       Q₂       Q₁       Q₀

  CLK 1: Input=1  → [1][0][0][0]
  CLK 2: Input=0  → [0][1][0][0]
  CLK 3: Input=1  → [1][0][1][0]
  CLK 4: Input=1  → [1][1][0][1]
  After 4 clocks: Q₃Q₂Q₁Q₀ = 1101 (reversed input order)

Note: The first bit entered (1) ends up at Q₀, and the last bit (1) at Q₃.

Draw the complete ALSU block diagram showing arithmetic unit, logic unit, shift unit, MUX selector, and function-select lines S₃S₂S₁S₀. Label all inputs (A, B, Cᵢₙ) and output F.

Refer to the ALSU diagram in Section C.8. Key points: A and B are n-bit operands. S₃S₂ select the unit (Arith/Logic/Shift). S₁S₀ select the operation within the unit. Cᵢₙ is used only by the arithmetic unit. The 4×1 MUX at the output selects which unit's result to send as F.

🔢 Numerical Problems (6)

Given R1 = 10101100 and R2 = 11001010, compute: (a) R1 ∧ R2 (b) R1 ∨ R2 (c) R1 ⊕ R2 (d) R̄1

(a) R1 ∧ R2 = 10001000
(b) R1 ∨ R2 = 11101110
(c) R1 ⊕ R2 = 01100110
(d) R̄1 = 01010011

Perform selective set on R = 10100011 to set bits 4 and 5 to 1 (without changing other bits). Show the mask and result.

Mask = 00110000 (bits 4,5 set to 1)
R ∨ Mask = 10110011 ∨ 00110000 → Wait, let me redo:
R = 10100011
R ∨ Mask = 10100011 ∨ 00110000 = 10110011
Bits 4,5 are now 1. Other bits unchanged. ✓

Perform two consecutive logical shift left operations on the 8-bit value 00110101. What is the result? What is the equivalent decimal multiplication?

Original: 00110101 = 53
After 1st LSL: 01101010 = 106 (53 × 2)
After 2nd LSL: 11010100 = 212 (53 × 4)
Two left shifts = multiply by 4. ✓

Given the signed 8-bit value 11010100 (= −44 in 2's complement), perform arithmetic shift right twice. Show the result and verify it equals ⌊−44/4⌋.

Original: 11010100 = −44
After 1st ASR: 11101010 = −22 (−44 ÷ 2)
After 2nd ASR: 11110101 = −11 (−22 ÷ 2)
⌊−44/4⌋ = −11 ✓ (Sign bit 1 is preserved in both shifts)

In an ALSU, function select S₃S₂S₁S₀ = 0010 with Cᵢₙ = 1. If A = 01010000 and B = 00110000, compute F.

S₃S₂ = 00 → Arithmetic unit
S₁S₀ = 10 → F = A + B̄ + Cᵢₙ
B̄ = 11001111
F = 01010000 + 11001111 + 1 = 00100000
This is A − B = 80 − 48 = 32 = 00100000 ✓

A common bus system has 16 registers. How many select lines does the MUX need? If each register is 32 bits wide, how many 16×1 MUX circuits are required?

Select lines = log₂(16) = 4 lines (S₃S₂S₁S₀)
MUX circuits needed = 32 (one 16×1 MUX per bit position)
Total: 32 MUX circuits, each being a 16×1 multiplexer.

🏭 Industry Application Problems (3)

A network interface card (NIC) receives data serially over Ethernet at 1 Gbps. It needs to present this data to the CPU's 64-bit bus in parallel. Which type of shift register is used? How many clock cycles to fill the register for one 64-bit transfer?

SIPO (Serial In Parallel Out) shift register is used.
Clock cycles needed = 64 (one bit loaded per clock cycle).
At 1 Gbps, each bit arrives in 1 ns, so 64 bits take 64 ns = 64 clock cycles.
After 64 clocks, all 64 bits are available simultaneously on parallel outputs for the CPU bus.

In an ARM Cortex-A78 processor (used in Qualcomm Snapdragon chips made at Qualcomm Hyderabad), the barrel shifter can perform any shift operation in a single clock cycle. Why is this faster than using a sequential shift register? How does the barrel shifter achieve this using MUX layers?

A sequential shift register shifts 1 bit per clock cycle. Shifting by k positions takes k clocks.
A barrel shifter uses log₂(n) layers of multiplexers. For 32-bit data, it uses 5 MUX layers.
Each layer either shifts by 2ⁱ positions or passes through, controlled by shift-amount bits.
Result: ANY shift amount (0–31) in ONE clock cycle, regardless of shift distance.
This is critical for ARM's single-cycle execution pipeline used in mobile SoCs designed in India.

ISRO's Chandrayaan-3 telemetry system packs 8 sensor readings (each 4 bits) into a single 32-bit register using insert operations. Describe the RTL sequence to insert the 3rd sensor reading (value 1010) into bits 8–11 of the register R1 without disturbing other bits.

Step 1: Create clear mask for bits 8-11
  Mask = 00000000 00000000 00001111 00000000
  B̄    = 11111111 11111111 11110000 11111111

Step 2: Clear bits 8-11
  R1 ← R1 ∧ B̄

Step 3: Position new value at bits 8-11
  New = 00000000 00000000 00001010 00000000  (1010 shifted left by 8)

Step 4: Insert
  R1 ← R1 ∨ New

Combined RTL: R1 ← (R1 ∧ B̄) ∨ (Sensor₃ shl 8)

🎯 GATE Practice Problems (5)

G1 — GATE CSE 2019 Style

The operation performed by R3 ← R1 + R̄2 + 1 is equivalent to:

R1 AND R2
R1 − R2
R1 + R2
R1 XOR R2

UnderstandGATE

✅ Answer: (B) R1 − R2. Adding the 1's complement (R̄2) plus 1 is the 2's complement method of subtraction. R̄2 + 1 = −R2, so R1 + (−R2) = R1 − R2.

G2 — GATE CSE 2020 Style

A bus system uses a 64-to-1 multiplexer. How many selection lines are required?

RememberGATE

✅ Answer: (B) 6. A 2ⁿ-to-1 MUX needs n select lines. 2⁶ = 64. So 6 select lines.

G3 — GATE CSE 2021 Style

The arithmetic shift right operation on signed number 11110010 gives:

01111001
11111001
11110001
01110010

ApplyGATE

✅ Answer: (B) 11111001. ASR preserves the sign bit (MSB=1). All bits shift right by 1: 1→1, 1→1, 1→1, 1→1, 0→0, 0→0, 1→0, 0→lost. Result: 11111001. The original was −14, result is −7.

G4 — GATE CSE 2022 Style

To selectively complement bits 2 and 5 of register A = 10110100, the mask B and operation should be:

B = 00100100, A ∧ B
B = 00100100, A ∨ B
B = 00100100, A ⊕ B
B = 11011011, A ∧ B

ApplyGATE

✅ Answer: (C). XOR with mask having 1s at positions 2 and 5 toggles exactly those bits. A⊕B = 10110100 ⊕ 00100100 = 10010000. Bits 2 and 5 are complemented, all others unchanged.

G5 — GATE CSE 2023 Style

In a common bus system with k registers, each n bits wide, using n multiplexers each of size k×1, the total number of MUX select lines required is:

n × log₂(k)
log₂(k)
k × n
n × k

AnalyzeGATE

✅ Answer: (B) log₂(k). All n multiplexers share the SAME select lines. Only log₂(k) select lines are needed to choose which of the k registers drives the bus. The same select signal controls all n MUXes simultaneously.

Section F

MCQ Assessment Bank — 30 Questions (Bloom's Mapped)

Remember / Identify (Q1–Q6)

A register is a group of:

Counters
Decoders
Flip-flops
Multiplexers

Remember

✅ Answer: (C) Flip-flops. A register is a group of flip-flops, each storing one bit of data.

The RTL statement R2 ← R1 means:

Delete R1 and store in R2
Copy contents of R1 into R2
Swap R1 and R2
Compare R1 and R2

Remember

✅ Answer: (B) Copy contents of R1 into R2. The arrow ← indicates the direction of data transfer. R1 (source) is not modified.

In RTL notation, M[AR] refers to:

The address register
The memory word at the address stored in AR
The multiplication of A and R
A memory array of AR size

Remember

✅ Answer: (B) The memory word at the address stored in AR. Square brackets denote memory access, and AR holds the address.

SIPO stands for:

Serial Input Parallel Output
Single Input Pair Output
Synchronous In Phase Operation
Serial In Pulse Out

Remember

✅ Answer: (A) Serial Input Parallel Output — a shift register where data enters one bit at a time and exits all bits simultaneously.

The four types of micro operations are:

Register transfer, arithmetic, logic, shift
Add, subtract, multiply, divide
AND, OR, XOR, NOT
Read, write, execute, store

Remember

✅ Answer: (A) Register transfer, arithmetic, logic, and shift. These are the four fundamental categories of micro operations in digital computing.

In a common bus system, which component selects which register places data on the bus?

Decoder
Multiplexer (MUX)
Encoder
Flip-flop

Remember

✅ Answer: (B) Multiplexer (MUX). The MUX select lines determine which register's output is connected to the shared bus.

Understand / Explain (Q7–Q12)

Why does R2 ← R1 NOT erase R1?

Because R1 is read-only
Because it's a copy operation — the source register is only read, not cleared
Because both registers share the same flip-flops
Because the clock prevents erasure

Understand

✅ Answer: (B). Register transfer reads the output of R1 (which doesn't change R1's state) and loads it into R2. R1 retains its value.

What is the purpose of the LOAD control signal in a register?

To reset the register to zero
To determine whether the register captures new input on the next clock edge
To select which bit to read
To connect the register to the ALU

Understand

✅ Answer: (B). When LOAD=1, the register captures input data on the clock edge. When LOAD=0, the register holds its current value regardless of inputs.

Why is a bus system preferred over point-to-point connections between registers?

It's faster
It reduces the number of wires from O(n²) to O(n)
It allows multiple simultaneous transfers
It eliminates the need for multiplexers

Understand

✅ Answer: (B). With k registers, point-to-point needs k(k−1) connections. A bus needs only k connections to the bus + MUX, drastically reducing wiring complexity.

Q10

What distinguishes arithmetic shift right from logical shift right?

Arithmetic shift right is faster
Arithmetic shift right preserves the sign bit (MSB), logical shift right fills MSB with 0
They are identical operations
Logical shift right preserves the sign bit

Understand

✅ Answer: (B). ASR copies the sign bit (MSB) back into the MSB position, preserving the sign of the number. LSR fills MSB with 0, treating the number as unsigned.

Q11

In memory read operation DR ← M[AR], what is the role of AR?

AR stores the data to be read
AR contains the address of the memory location to be read
AR performs the read operation
AR stores the result of the read

Understand

✅ Answer: (B). AR (Address Register) holds the memory address. The data at that address flows from memory into DR (Data Register).

Q12

Why is circular shift useful in cryptographic algorithms?

It destroys the data permanently
No bits are lost — all information is preserved while rearranging bit positions
It's the same as addition
It only works on prime-length registers

Understand

✅ Answer: (B). Unlike logical shifts where bits fall off, circular shifts preserve all bits by wrapping them around. This reversible property is essential in encryption algorithms like AES and DES.

Apply / Compute (Q13–Q18)

Q13

If R1 = 11001010 and R2 = 10110011, what is R1 ∧ R2?

10000010
11111011
01111001
10001000

Apply

✅ Answer: (A) 10000010. AND each bit pair: 1∧1=1, 1∧0=0, 0∧1=0, 0∧1=0, 1∧0=0, 0∧0=0, 1∧1=1, 0∧1=0.

Q14

Logical shift left of 01011010 gives:

10110100
00101101
01011010
10110101

Apply

✅ Answer: (A) 10110100. All bits shift left by 1. MSB (0) is lost, LSB filled with 0.

Q15

Circular shift right of 10000001 gives:

01000000
11000000
11000000
01000001

Apply

✅ Answer: (B) 11000000. The LSB (1) wraps to MSB. All other bits shift right by 1. Result: 1_1000000 = 11000000.

Q16

To selectively set bits 0 and 3 of R = 10100100, the mask and operation are:

Mask = 00001001, R ∧ Mask
Mask = 00001001, R ∨ Mask
Mask = 00001001, R ⊕ Mask
Mask = 11110110, R ∧ Mask

Apply

✅ Answer: (B). Selective set uses OR. Mask has 1s at positions to set (bits 0,3 = 00001001). R ∨ 00001001 = 10101101.

Q17

In the ALSU, S₃S₂S₁S₀ = 0101 selects:

Addition (A + B)
OR (A ∨ B)
XOR (A ⊕ B)
Shift left

Apply

✅ Answer: (B). S₃S₂ = 01 selects the logic unit. S₁S₀ = 01 selects the second logic operation, which is OR (A ∨ B).

Q18

What is the result of R1 ← R1 + R̄1 + 1?

R1 = 0 (all zeros)
R1 = all ones
R1 unchanged
R1 = 1

Apply

✅ Answer: (A) R1 = 0. R1 + R̄1 = all 1s (111...1). Adding 1 causes overflow, resulting in 000...0 (with carry out discarded in an n-bit register).

Analyze / Compare (Q19–Q24)

Q19

Which shift register type is needed to convert parallel CPU data to serial data for USB transmission?

SISO
SIPO
PISO
PIPO

Analyze

✅ Answer: (C) PISO. Parallel data from the CPU bus is loaded into all flip-flops simultaneously, then shifted out one bit at a time through the serial output for USB/UART transmission.

Q20

For a system with 32 registers, how many MUX select lines are needed for the common bus?

Analyze

✅ Answer: (B) 5. Select lines = log₂(32) = 5. With 5 select lines, we can choose any one of 2⁵ = 32 registers.

Q21

Three consecutive logical shift left operations on an 8-bit value are equivalent to:

Multiplying by 3
Multiplying by 6
Multiplying by 8
Multiplying by 16

Analyze

✅ Answer: (C) Multiplying by 8. Each left shift = ×2. Three shifts = ×2³ = ×8. (Assuming no overflow)

Q22

Which operation is used to test if a specific bit is 1 without modifying the register?

Selective set (OR)
Selective clear (AND complement)
Mask operation (AND with mask, check result)
Complement (NOT)

Analyze

✅ Answer: (C). AND the register with a mask having 1 only at the bit position to test. If result is non-zero, that bit is 1. This is a non-destructive test operation.

Q23

If both memory read and memory write use the same data bus, what prevents data collision?

They use different clock speeds
Read and write control signals are mutually exclusive — only one is active at a time
They use separate address registers
Memory can handle simultaneous read and write

Analyze

✅ Answer: (B). The READ and WRITE control signals are never both active simultaneously. This ensures data flows in only one direction on the bus at any given time.

Q24

What advantage does a barrel shifter have over a sequential shift register in ALU design?

It uses fewer transistors
It can shift by any amount in one clock cycle instead of one bit per cycle
It only works with 8-bit data
It doesn't need control signals

Analyze

✅ Answer: (B). A barrel shifter uses MUX layers to perform any shift amount in O(1) time, while a sequential shifter needs k cycles for k-bit shift.

Evaluate / Justify (Q25–Q27)

Q25

A student claims "Arithmetic shift left is different from logical shift left." Is this correct?

Yes, arithmetic shift left preserves the sign bit
No, both operations are identical — shift all bits left, fill LSB with 0
Yes, arithmetic shift left fills MSB with 1
No, arithmetic shift left doesn't exist

Evaluate

✅ Answer: (B). Arithmetic shift left and logical shift left produce the same result: all bits move left, LSB is filled with 0. The distinction only exists for right shifts (sign preservation).

Q26

Why can't two registers simultaneously drive the common bus?

The clock can only trigger one register
Different voltage levels from two sources would cause bus contention (short circuit)
MUX has only one output
Both B and C

Evaluate

✅ Answer: (D). Both electrical (bus contention causes undefined voltages) and logical (MUX selects exactly one input) reasons prevent simultaneous driving. This is why the MUX exists.

Q27

Is the operation R1 ← R1 ⊕ R1 useful? What does it produce?

It doubles R1
It complements R1
It always produces all zeros — a quick way to clear a register
It produces all ones

Evaluate

✅ Answer: (C). Any value XORed with itself produces 0. This is a common hardware trick to clear a register in a single operation (used by x86 compilers: XOR EAX, EAX).

Create / Design (Q28–Q30)

Q28

To swap two registers R1 and R2 without a temporary register, the correct RTL sequence using XOR is:

R1←R1⊕R2, R2←R1⊕R2, R1←R1⊕R2
R1←R1∧R2, R2←R1∨R2, R1←R1∧R2
R1←R1+R2, R2←R1−R2, R1←R1−R2
Both A and C

Create

✅ Answer: (D). Both XOR swap and arithmetic swap work without a temporary register. XOR swap: Step 1: R1=R1⊕R2, Step 2: R2=R1⊕R2=(R1⊕R2)⊕R2=R1, Step 3: R1=R1⊕R2=(R1⊕R2)⊕R1=R2.

Q29

To implement R3 ← R1 − R2 using only addition and complement operations, the correct design is:

R3 ← R1 + R2
R3 ← R1 + R̄2 + 1
R3 ← R̄1 + R2 + 1
R3 ← R1 + R̄2

Create

✅ Answer: (B). 2's complement subtraction: −R2 = R̄2 + 1. Therefore R1 − R2 = R1 + R̄2 + 1. This is how ALUs implement subtraction using only an adder and complementer.

Q30

Design an RTL sequence to multiply the contents of R1 by 5 using only shift and add operations:

R2 ← shl R1; R2 ← shl R2; R1 ← R1 + R2
R2 ← R1; R1 ← shl R1; R1 ← shl R1; R1 ← R1 + R2
R1 ← shl R1; R1 ← shl R1; R1 ← R1 + R1
R2 ← shl R1; R1 ← R1 + R2

Create

✅ Answer: (B). R2 saves original R1. Two left shifts on R1 = R1×4. Then R1 + R2 = 4×original + original = 5×original. This is how hardware multipliers optimize constant multiplication.

Section G

Short Answer Questions (8)

SA1

Define a register and explain the role of the LOAD signal. (3 marks)

Register: A register is a group of flip-flops used to store binary information. An n-bit register consists of n flip-flops and can store n bits of data simultaneously.

LOAD signal: The LOAD control signal determines whether the register accepts new data. When LOAD = 1, the register captures the input data on the next clock edge. When LOAD = 0, the register retains its current contents regardless of input changes. This makes the register "selective" — it only updates when explicitly commanded to do so.

SA2

Explain the difference between R2 ← R1 and P: R2 ← R1. (3 marks)

R2 ← R1: Unconditional transfer. The contents of R1 are copied into R2 on every clock edge, regardless of any condition.

P: R2 ← R1: Conditional transfer. The transfer occurs ONLY when control variable P = 1. If P = 0, R2 retains its old value. The condition P is checked at the clock edge — both P = 1 and the clock edge must coincide for the transfer to happen. This is implemented by ANDing P with the CLK signal to generate the LOAD input for R2.

SA3

What is a common bus system? Why is it preferred over direct connections? (4 marks)

Common Bus System: A shared set of wires (data path) that connects all registers through multiplexers. Only one register can place data on the bus at a time (selected by MUX control lines), and any register with LOAD enabled can read from the bus.

Why preferred:
1. Reduced wiring: k registers need only k connections to the bus, versus k(k−1) point-to-point connections
2. Scalability: Adding a new register requires only connecting it to the bus, not to every other register
3. Simpler control: Only log₂(k) select lines needed to choose the source register
4. Trade-off: Slower (only one transfer per clock cycle) but much simpler and cheaper hardware

SA4

Describe the four selective logic operations with one example each. (5 marks)

1. Selective Set (OR): Sets specific bits to 1. R = 10100011, Mask = 00001100 → R ∨ Mask = 10101111. Bits 2,3 set to 1.

2. Selective Clear (AND complement): Clears specific bits to 0. R = 10101111, Mask = 00001100, B̄ = 11110011 → R ∧ B̄ = 10100011. Bits 2,3 cleared.

3. Selective Complement (XOR): Toggles specific bits. R = 10100011, Mask = 00001100 → R ⊕ Mask = 10101111. Bits 2,3 flipped.

4. Insert (Clear then Set): Replaces specific bits with new values. First clear target bits using AND complement, then set new values using OR. R = 10100011, clear bits 2,3, insert 10 → (R ∧ 11110011) ∨ 00001000 = 10101011.

SA5

Compare logical shift right and arithmetic shift right with a numerical example. (4 marks)

Logical Shift Right (LSR): All bits shift right by 1. MSB is filled with 0. Used for unsigned division by 2.
Example: 11010110 → 01101011 (214 → 107 unsigned)

Arithmetic Shift Right (ASR): All bits shift right by 1. MSB retains its original value (sign preservation). Used for signed division by 2.
Example: 11010110 → 11101011 (−42 → −21 signed)

Key difference: For positive numbers (MSB=0), both produce the same result. For negative numbers (MSB=1), LSR incorrectly changes the sign to positive, while ASR correctly preserves the negative sign.

SA6

List and briefly describe the four types of shift registers (SISO, SIPO, PISO, PIPO). (4 marks)

1. SISO (Serial In Serial Out): Data enters and exits one bit at a time. Used as delay lines — data takes n clock cycles to pass through n flip-flops.

2. SIPO (Serial In Parallel Out): Data enters one bit at a time but all bits are available simultaneously at the output. Used for serial-to-parallel conversion (e.g., UART receiver).

3. PISO (Parallel In Serial Out): All bits are loaded at once, then shifted out one at a time. Used for parallel-to-serial conversion (e.g., UART transmitter).

4. PIPO (Parallel In Parallel Out): All bits loaded and read simultaneously. Acts as a buffer or temporary storage register. Used in pipeline stages and data latches.

SA7

Explain how subtraction is implemented using addition in an ALU. (3 marks)

Subtraction using 2's complement addition:
To compute A − B, the ALU performs: A + B̄ + 1

Steps:
1. Take the 1's complement of B (invert all bits): B̄
2. Add 1 to get the 2's complement: B̄ + 1 = −B
3. Add A + (−B) = A − B

This means the ALU only needs an adder and a complementer — no separate subtraction circuit is required. The Cᵢₙ (carry input) provides the +1.

SA8

What are the function-select lines in an ALSU? How do S₃S₂ and S₁S₀ work together? (4 marks)

Function-select lines (S₃S₂S₁S₀): 4-bit control input that determines which operation the ALSU performs.

Two-level selection:
• S₃S₂ (Unit Select): Selects which sub-unit produces the output:
- 00 = Arithmetic unit (add, subtract, increment, etc.)
- 01 = Logic unit (AND, OR, XOR, NOT)
- 10 = Shift unit (logical, circular, arithmetic shifts)

• S₁S₀ (Operation Select): Selects the specific operation within the chosen unit. For example, in the logic unit: 00=AND, 01=OR, 10=XOR, 11=NOT.

Additionally, Cᵢₙ (carry input) acts as an extra selector for arithmetic operations, effectively doubling the number of arithmetic functions (e.g., Transfer A vs Increment A).

Section H

Long Answer Questions (3)

📝 LA1: Explain Register Transfer Language (RTL) with all notation rules, 10 operation examples, and conditional transfer with timing diagram (10 marks)

Model Answer Outline:

Definition of RTL: A symbolic notation used to describe the micro operations and data transfers between registers in a digital system. It specifies which register receives data (destination ← source), under what conditions, and what operation is performed.
Notation rules (6 rules): Uppercase letters for registers, ← for transfer, comma for simultaneous operations, colon for conditions, parentheses for bit selection, brackets for memory access.
10 operation examples:
- R2 ← R1 (simple transfer)
- P: R2 ← R1 (conditional transfer)
- R1 ← R1 + R2 (addition)
- R3 ← R1 + R̄2 + 1 (subtraction via 2's complement)
- R1 ← R1 ∧ R2 (AND), R1 ← R1 ∨ R2 (OR), R1 ← R1 ⊕ R2 (XOR)
- R1 ← shl R1, R1 ← shr R1 (shifts)
- DR ← M[AR] (memory read), M[AR] ← DR (memory write)
Conditional transfer with timing diagram: Show P: R2 ← R1 with clock pulses, P signal, and the exact clock edge where transfer occurs. Explain that P must be 1 BEFORE the clock edge.
Hardware implementation: P signal ANDed with CLK to generate the LOAD pulse for the destination register.

📝 LA2: Explain the Common Bus System with a diagram for 4 registers using multiplexers. Describe memory read and write operations with RTL. (10 marks)

Model Answer Outline:

Problem: k registers need k(k−1) direct connections — impractical for large systems
Solution: Common bus — shared data path using MUX to select source register
Diagram: 4 registers (R0-R3) connected through n-bit 4×1 MUX. 2 select lines (S₁S₀). Show bus and LOAD signals for each register.
Number of MUXes: For n-bit registers, need n separate 4×1 MUX circuits. All share the same S₁S₀ select lines.
Transfer example: R3 ← R1 requires S₁S₀ = 01 (select R1 onto bus) and R3 LOAD = 1.
Memory Read (DR ← M[AR]): AR provides address to memory address bus, READ control activated, data from memory cell placed on data bus, DR captures data on clock edge.
Memory Write (M[AR] ← DR): AR provides address, DR provides data on data bus, WRITE control activated, memory cell at AR address stores the data.
Advantages: Reduced wiring complexity, easier to scale, simpler control logic.
Disadvantage: Only one transfer per clock cycle (bus bottleneck).

📝 LA3: Design and explain the Arithmetic Logic Shift Unit (ALSU) with complete operation table. Show how subtraction and all shift types are performed. (12 marks)

Model Answer Outline:

ALSU Structure: Three sub-units — Arithmetic Unit, Logic Unit, Shift Unit — with output MUX
Block Diagram: Inputs A, B (n-bit), function select S₃S₂S₁S₀, carry input Cᵢₙ, output F (n-bit)
S₃S₂ Unit Selection: 00 = Arithmetic, 01 = Logic, 10 = Shift
Complete Operation Table: All 16+ operations with S₃S₂S₁S₀ and Cᵢₙ values
Arithmetic operations: Transfer, Increment, Add, Add with carry, A+B̄, Subtract (A−B = A+B̄+1), Decrement
Subtraction explained: A − B = A + 2's complement of B = A + B̄ + 1. The complementer inverts B, Cᵢₙ = 1 adds the extra 1.
Logic operations: AND, OR, XOR, NOT (complement)
Shift operations:
- Logical shift left/right: 0 fills vacated bit
- Circular shift left/right: lost bit wraps around
- Arithmetic shift right: sign bit preserved
MUX design: 4×1 MUX at output selects Arith/Logic/Shift result based on S₃S₂
Status flags: Carry out, Zero flag, Sign flag, Overflow flag generated from arithmetic unit results

Section I

Industry Spotlight — A Day in the Life

👨‍💻 Rajesh Kumar, 30 — RTL Design Engineer at Qualcomm India, Hyderabad

Background: B.Tech ECE from NIT Warangal. Joined Qualcomm as a campus hire in 2018. Worked his way up from junior verification engineer to RTL design engineer. Designs register files and data-path logic for Snapdragon mobile SoCs.

A Typical Day:

9:00 AM — Morning standup with the CPU micro-architecture team. Review overnight regression test results for the register file design.

10:00 AM — Write Verilog RTL code for a new 64-entry register file with 3 read ports and 2 write ports. Implement bypass logic for back-to-back register transfers (write-then-read in the same cycle).

11:30 AM — Run synthesis to check if the register file meets timing at 3.2 GHz target frequency. Debug a critical path through the MUX tree.

1:00 PM — Lunch at Qualcomm's Hyderabad campus. Discuss a new power-gating technique for idle registers with a colleague from the power team.

2:00 PM — Code review for a junior engineer's shift-unit design. Spot a bug: arithmetic shift right isn't preserving the sign bit correctly for 16-bit mode.

4:00 PM — Write SystemVerilog assertions (SVA) to formally verify that all register transfer operations produce correct results under all corner cases.

5:30 PM — Architecture review meeting: discuss adding a barrel shifter to the ALSU design for the next-gen Snapdragon chip targeting 4 nm process.

Detail	Info
Tools Used Daily	Verilog/SystemVerilog, Synopsys Design Compiler, VCS, Verdi, Python scripting
Entry Salary (2024)	₹12–18 LPA (NIT/IIT campus)
Mid-Level (3–5 yrs)	₹20–35 LPA
Senior (7+ yrs)	₹40–70 LPA
Companies Hiring in India	Qualcomm, Intel, AMD, Samsung R&D, ARM, MediaTek, Texas Instruments, Synopsys, Cadence, ISRO
Required Skills	Digital design, Verilog HDL, RTL coding, computer architecture, VLSI fundamentals

Career Insight: RTL design is one of the highest-paying engineering roles in India. Qualcomm Hyderabad, Intel Bangalore, and Samsung Noida hire 500+ VLSI engineers annually from NITs and IITs. The register transfer concepts you're learning now are EXACTLY what these engineers code in Verilog every day. Start learning Verilog alongside this course!

Section J

Earn With It — GATE Coaching & Freelance Opportunities

💰 Your Earning Path After This Chapter

Portfolio Piece: "8-Bit Shift Register Simulator in Python" + comprehensive RTL trace solutions for GATE-level problems. Host on GitHub.

Earning Opportunities:

• GATE coaching assistance — Help juniors with COA register transfer topic — ₹500–₹1,000/session on Chegg/Doubtnut

• Create GATE COA YouTube/Unacademy micro-lectures — Register Transfer & Micro Ops (high search volume topic)

• Freelance Verilog/VHDL assignments — write RTL code for university assignments — ₹1,000–₹5,000/project on Chegg Study

• Build digital design simulators for engineering colleges — ₹5,000–₹15,000/project

Opportunity	Platform	Earning Potential
GATE COA tutoring	Chegg, Doubtnut, WhatsApp groups	₹3,000–₹8,000/month
YouTube GATE prep videos	YouTube, Unacademy	₹5,000–₹30,000/month (with traction)
Verilog assignments	Chegg Study, Freelancer	₹1,000–₹5,000/project
Digital design simulators	Direct college contracts	₹5,000–₹15,000/project
GATE full-length coaching	Toppr, BYJU's, offline	₹10,000–₹25,000/month

GATE CSE consistently asks 2–3 marks on register transfer and micro operations. Mastering this chapter thoroughly positions you as a GATE subject expert in COA — a topic many students struggle with. Being the "go-to" person for this topic in your college or coaching centre can generate consistent tutoring income.

Section K

Chapter Summary & Unit Map

📋 Key Takeaways — Unit 2: Register Transfer & Micro Operations

Register = group of flip-flops with LOAD control and CLK synchronization. n-bit register has n flip-flops.
Register Transfer (R2 ← R1) copies source to destination without erasing source. Conditional: P: R2 ← R1.
RTL Notation uses ←, commas (simultaneous), colons (conditions), brackets (memory), parentheses (bit select).
Common Bus = shared data path via MUX. Reduces k(k−1) wires to k connections + log₂(k) select lines.
Memory ops: Read: DR ← M[AR]. Write: M[AR] ← DR. AR = address, DR = data.
Logic micro ops: AND (selective clear), OR (selective set), XOR (selective complement), NOT (full complement).
Shift registers: SISO (delay), SIPO (serial→parallel), PISO (parallel→serial), PIPO (buffer).
Shift micro ops: Logical (0 fill), Circular (wrap), Arithmetic right (sign preserve). Left shift = ×2.
ALSU: S₃S₂ selects unit (Arith/Logic/Shift), S₁S₀ selects operation within unit. Cᵢₙ adds +1 for arithmetic.
Subtraction = Addition of 2's complement: A − B = A + B̄ + 1. No separate subtractor needed.

🗺️ Unit Map — Concept Hierarchy

  ┌────────────────────────────────────────────────────────────────────┐
  │           UNIT 2: REGISTER TRANSFER & MICRO OPERATIONS            │
  ├────────────────────────────────────────────────────────────────────┤
  │                                                                    │
  │  ┌──────────────┐    ┌─────────────────┐    ┌──────────────────┐  │
  │  │  REGISTERS   │    │ REGISTER        │    │    BUS SYSTEM    │  │
  │  │              │    │ TRANSFER        │    │                  │  │
  │  │ • Flip-flops │    │                 │    │ • Common bus     │  │
  │  │ • LOAD/CLK   │    │ • R2 ← R1      │    │ • MUX select     │  │
  │  │ • Parallel   │    │ • P: R2 ← R1   │    │ • Memory R/W     │  │
  │  │   load       │    │ • RTL notation  │    │ • DR ← M[AR]    │  │
  │  └──────┬───────┘    └───────┬─────────┘    └────────┬─────────┘  │
  │         │                    │                       │            │
  │         └────────────────────┼───────────────────────┘            │
  │                              │                                    │
  │                              ▼                                    │
  │              ┌───────────────────────────────┐                    │
  │              │      MICRO OPERATIONS         │                    │
  │              ├───────────┬─────────┬─────────┤                    │
  │              │           │         │         │                    │
  │              ▼           ▼         ▼         ▼                    │
  │         ┌─────────┐ ┌────────┐ ┌───────┐ ┌───────────┐          │
  │         │ARITHMETIC│ │ LOGIC  │ │ SHIFT │ │  SHIFT    │          │
  │         │          │ │        │ │ REGS  │ │  MICRO    │          │
  │         │ Add      │ │ AND    │ │       │ │  OPS      │          │
  │         │ Subtract │ │ OR     │ │ SISO  │ │           │          │
  │         │ Incr/Decr│ │ XOR    │ │ SIPO  │ │ Logical   │          │
  │         │ Transfer │ │ NOT    │ │ PISO  │ │ Circular  │          │
  │         │          │ │        │ │ PIPO  │ │ Arithmetic│          │
  │         └────┬─────┘ └───┬────┘ └───────┘ └─────┬─────┘          │
  │              │           │                      │                │
  │              └───────────┼──────────────────────┘                │
  │                          ▼                                       │
  │              ┌───────────────────────┐                           │
  │              │   ALSU (Combined)     │                           │
  │              │                       │                           │
  │              │ S₃S₂S₁S₀ + Cᵢₙ      │                           │
  │              │ Function Select       │                           │
  │              └───────────────────────┘                           │
  └────────────────────────────────────────────────────────────────────┘

Section L

Earning Checkpoint — Self-Assessment

Skill / Concept	Tool / Method	Evidence of Mastery	Ready to Earn?
Register basics	Conceptual	Can draw n-bit register with LOAD/CLK	✅ Can explain in GATE coaching
RTL notation	Pen & paper	Can write & trace any RTL sequence	✅ Can tutor juniors
Bus system design	Diagram	Can draw MUX-based common bus	✅ Interview-ready concept
Logic micro ops	Binary computation	Can perform selective set/clear/complement/insert	✅ Can solve GATE numericals
Shift registers (4 types)	Diagram + trace	Can trace SISO/SIPO/PISO/PIPO data flow	✅ Can create teaching material
Shift micro ops (5 types)	Binary computation	Can predict output for any 8-bit shift	✅ Can solve any GATE shift question
ALSU operation table	Table + diagram	Can map S₃S₂S₁S₀ to operations	✅ GATE 2-3 mark question ready
Python simulator	Python code	Working 8-bit shift register simulator	✅ Portfolio piece on GitHub
Memory operations	RTL notation	Can explain DR ← M[AR] and M[AR] ← DR	✅ Can teach in college lab

Minimum Viable Earning Setup after this chapter: Master RTL traces + shift operations + ALSU table → Start GATE COA tutoring (₹500–₹1,000/session). Build Python simulator → Upload to GitHub → Show as portfolio in interviews. Create 3–5 GATE problem solution videos → Upload to YouTube.

✅ Unit 2 complete. Ready for Unit 3: Basic Computer Organization!

[QR: Link to EduArtha video tutorial — Register Transfer & Micro Operations]