Computer Organization & Architecture

Unit 1: Basics of Digital Systems

From logic gates to flip-flops — master combinational and sequential circuits that form the foundation of every computer ever built.

⏱️ 5 hrs theory + 3 hrs lab | 🎯 GATE ~3 marks | 💰 ₹6–12 LPA | 🖥️ ISRO PSLV

💼 Jobs this unlocks: VLSI Design Engineer (₹6–12 LPA) | Embedded Systems Developer (₹5–10 LPA) | GATE/ISRO/DRDO PSU roles

Section A

Opening Hook — The Digital Brain Behind ISRO's PSLV

🚀 PSLV-C58: How Digital Circuits Put India in Orbit

On January 1, 2024, ISRO's PSLV-C58 thundered into the sky carrying the XPoSat satellite. Inside the rocket's flight computer, thousands of digital circuits executed flawlessly at 100 MHz — making life-or-death decisions every 10 nanoseconds.

Combinational circuits computed real-time thrust vector calculations for stage separation — pure logic, no memory, instantaneous output. When the first stage burned out at T+113 seconds, a combinational decoder triggered the pyrotechnic bolts that separated the booster. One wrong gate? The rocket tumbles into the Bay of Bengal.

Sequential circuits tracked the rocket's state — "Are we in Stage 1? Stage 2? Coasting? Payload separation?" — using flip-flops that remember the current state and transition only on clock edges. The flight computer's state machine cycled through 47 distinct states from launch to orbit insertion.

What if YOU understood these circuits? What if you could design the logic that decides when a 320-tonne rocket drops its booster? That's exactly what this unit teaches you — the same fundamentals used by ISRO, Intel, and Qualcomm engineers.

🇮🇳 ISRO🇮🇳 DRDO🇮🇳 BHELIntel IndiaQualcomm HyderabadTexas Instruments Bangalore

Every smartphone you use has over 15 billion transistors — all organized into combinational and sequential circuits. Apple's M2 chip has 20 billion transistors, each a tiny switch doing exactly what you'll learn in this chapter: AND, OR, NOT, flip, flop. The principles are the same whether it's a ₹500 calculator or a ₹5 crore satellite computer.

Section B

Learning Outcomes — Bloom's Taxonomy Mapped (12 Outcomes)

Bloom's Level	Learning Outcome
🔵 Remember	LO1: List the five functional units of a computer and identify the role of each unit
🔵 Remember	LO2: State the truth tables for all basic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) and standard combinational circuits
🟢 Understand	LO3: Explain the difference between combinational and sequential circuits with real-world analogies
🟢 Understand	LO4: Describe the operation of SR, D, JK, and T flip-flops using characteristic equations and timing diagrams
🟡 Apply	LO5: Design a Half Adder and Full Adder from truth tables and draw their gate-level circuits
🟡 Apply	LO6: Construct a 4-bit Ripple Carry Adder by cascading Full Adders and trace binary addition through it
🟠 Analyze	LO7: Compare SR, D, JK, and T flip-flops on parameters like race condition, toggling, and input constraints
🟠 Analyze	LO8: Analyze the propagation delay issue in Ripple Carry Adders and contrast with Carry Look-Ahead Adders
🔴 Evaluate	LO9: Evaluate which flip-flop type is most suitable for a given application (counter, register, frequency divider)
🔴 Evaluate	LO10: Justify the use of MUX as a universal logic element and assess trade-offs vs discrete gates
🟣 Create	LO11: Design a 3-bit synchronous counter using JK flip-flops with complete state table and circuit diagram
🟣 Create	LO12: Build a Python simulator that generates truth tables for any n-input combinational circuit

Section C

Concept Explanation — Digital Systems from Scratch

1. The 5-Unit Computer Model

Every computer — from a ₹500 Arduino to a ₹5 crore supercomputer — has exactly five functional units. Think of them as five departments in a factory, each with a specific job, connected by highways called buses.

🖥️ The Five Functional Units of a Computer

  ┌─────────────────────────────────────────────────────────────┐
  │                      COMPUTER SYSTEM                        │
  │                                                             │
  │  ┌───────────┐                          ┌───────────────┐   │
  │  │           │    Data/Address Bus       │               │   │
  │  │   INPUT   │◄────────────────────────►│    MEMORY     │   │
  │  │   UNIT    │                          │  (RAM / ROM)  │   │
  │  │           │                          │               │   │
  │  │ Keyboard  │                          │  Stores Data  │   │
  │  │ Mouse     │                          │  & Programs   │   │
  │  │ Scanner   │                          │               │   │
  │  └─────┬─────┘                          └───────┬───────┘   │
  │        │                                        │           │
  │        │          ┌───────────────┐              │           │
  │        │          │  CONTROL UNIT │              │           │
  │        └─────────►│     (CU)      │◄─────────────┘           │
  │                   │               │                         │
  │                   │ Fetches &     │      Control Bus         │
  │                   │ Decodes       │◄───────────────────┐    │
  │                   │ Instructions  │                    │    │
  │                   └───────┬───────┘                    │    │
  │                           │                            │    │
  │                           │ Control Signals            │    │
  │                           ▼                            │    │
  │                   ┌───────────────┐              ┌─────┴───┐│
  │                   │     ALU       │              │  OUTPUT  ││
  │                   │ (Arithmetic   │             │  UNIT    ││
  │                   │  Logic Unit)  │─────────────►│         ││
  │                   │               │              │ Monitor  ││
  │                   │ +, -, ×, ÷    │              │ Printer  ││
  │                   │ AND, OR, NOT  │              │ Speaker  ││
  │                   └───────────────┘              └─────────┘│
  │                                                             │
  │  ═══════════════════════════════════════════════════════     │
  │   Three Buses: Data Bus, Address Bus, Control Bus           │
  └─────────────────────────────────────────────────────────────┘

Input Unit

Accepts data and instructions from the outside world. Examples: keyboard, mouse, scanner, microphone, touchscreen. In ISRO's PSLV, sensors (accelerometers, gyroscopes) act as input devices feeding flight data.

Memory Unit

Stores data and instructions. Primary memory (RAM — volatile, fast) holds currently executing programs. Secondary memory (HDD/SSD — non-volatile, slower) stores permanent data. ROM holds firmware/BIOS.

Arithmetic Logic Unit (ALU)

The calculator of the computer. Performs arithmetic operations (+, −, ×, ÷) and logical operations (AND, OR, NOT, XOR). Every computation ultimately happens here.

Control Unit (CU)

The brain's manager. Fetches instructions from memory, decodes them, and sends control signals to other units. It coordinates everything — like a traffic police officer at a busy crossing.

Output Unit

Presents processed results to the user. Examples: monitor, printer, speaker, LED display. In PSLV, the output includes telemetry signals sent to the ground station.

System Buses

Data Bus: Carries actual data between units (bidirectional). Address Bus: Carries memory addresses (unidirectional — CPU to memory). Control Bus: Carries control signals like read/write, clock, interrupt.

India's PARAM Siddhi supercomputer (63rd in TOP500, 2023) at C-DAC Pune has the same 5-unit architecture — just scaled massively. It has thousands of ALUs (GPU cores), terabytes of memory, and high-speed interconnects as buses. The fundamental structure you just learned applies at every scale.

2. Combinational Circuits — No Memory, Pure Logic

Definition: A combinational circuit's output depends only on its current inputs. It has no memory, no feedback, no clock. Change the input → output changes instantly (after gate delay).

Analogy — The Vending Machine: A combinational circuit is like a vending machine. You press ₹20 button + "Cold Coffee" → out comes cold coffee. The machine doesn't remember what you bought yesterday. Same input always produces same output. No history, no state.

2.1 Half Adder

The simplest arithmetic circuit. Adds two single bits (A and B) and produces a Sum (S) and a Carry (C).

  HALF ADDER — Truth Table
  ┌─────┬─────┬──────┬───────┐
  │  A  │  B  │ Sum  │ Carry │
  ├─────┼─────┼──────┼───────┤
  │  0  │  0  │  0   │   0   │
  │  0  │  1  │  1   │   0   │
  │  1  │  0  │  1   │   0   │
  │  1  │  1  │  0   │   1   │
  └─────┴─────┴──────┴───────┘

  Equations:  Sum = A ⊕ B  (XOR)
              Carry = A · B  (AND)

  HALF ADDER — Gate Diagram
              ┌─────────┐
   A ────────►│         │
              │   XOR   ├──────► Sum (S)
   B ────┬───►│         │
         │    └─────────┘
         │
         │    ┌─────────┐
   A ───►│───►│         │
              │   AND   ├──────► Carry (C)
   B ───►│───►│         │
              └─────────┘

2.2 Full Adder

Adds three single bits: A, B, and a Carry-In (Cin) from the previous stage. Produces Sum and Carry-Out (Cout). This is the building block for multi-bit adders.

  FULL ADDER — Truth Table
  ┌─────┬─────┬──────┬──────┬──────┐
  │  A  │  B  │ Cin  │ Sum  │ Cout │
  ├─────┼─────┼──────┼──────┼──────┤
  │  0  │  0  │  0   │  0   │  0   │
  │  0  │  0  │  1   │  1   │  0   │
  │  0  │  1  │  0   │  1   │  0   │
  │  0  │  1  │  1   │  0   │  1   │
  │  1  │  0  │  0   │  1   │  0   │
  │  1  │  0  │  1   │  0   │  1   │
  │  1  │  1  │  0   │  0   │  1   │
  │  1  │  1  │  1   │  1   │  1   │
  └─────┴─────┴──────┴──────┴──────┘

  Equations:  Sum  = A ⊕ B ⊕ Cin
              Cout = (A · B) + (Cin · (A ⊕ B))

  FULL ADDER — Gate Diagram (using 2 Half Adders + OR)

   A ──────►┌──────────┐
            │  HALF    │──── S1 ────►┌──────────┐
   B ──────►│  ADDER 1 │             │  HALF    │──────► Sum
            │          │──── C1      │  ADDER 2 │
            └──────────┘      │ Cin─►│          │──C2─┐
                              │      └──────────┘     │
                              │                       │
                              │    ┌──────┐           │
                              └───►│      │           │
                                   │  OR  ├──────────►Cout
                              ┌───►│      │
                              │    └──────┘
                              C2

2.3 4:1 Multiplexer (MUX)

A MUX selects one of several input lines and forwards it to a single output. Think of it as a railway track switch — 4 tracks converge into 1, and the switchman (select lines) decides which train passes.

  4:1 MUX — Block Diagram

   I0 ──────►┌───────────────┐
   I1 ──────►│               │
   I2 ──────►│   4:1 MUX     ├──────► Y (Output)
   I3 ──────►│               │
              └───────┬───────┘
                      │
               S1 ────┘──── S0
            (Select Lines)

  Truth Table:
  ┌─────┬─────┬────────┐
  │ S1  │ S0  │ Output │
  ├─────┼─────┼────────┤
  │  0  │  0  │   I0   │
  │  0  │  1  │   I1   │
  │  1  │  0  │   I2   │
  │  1  │  1  │   I3   │
  └─────┴─────┴────────┘

  Equation: Y = S1'·S0'·I0 + S1'·S0·I1 + S1·S0'·I2 + S1·S0·I3

GATE Favourite: A 2ⁿ:1 MUX can implement ANY n-variable Boolean function. This makes MUX a universal logic element. To implement f(A,B) using a 4:1 MUX, connect A and B to select lines, then connect the function's output column values to I0, I1, I2, I3. This trick saves you in GATE 2-mark questions.

2.4 Decoder (2:4)

A decoder takes an n-bit binary input and activates exactly one of 2ⁿ output lines. Think of it as a hotel keycard system — your room number (binary input) opens exactly one door (output).

  2:4 DECODER — Block Diagram & Truth Table

   A ──────►┌───────────────┐──────► D0 = A'·B'
   B ──────►│  2:4 DECODER  │──────► D1 = A'·B
             │               │──────► D2 = A·B'
             │               │──────► D3 = A·B
             └───────────────┘

  Truth Table:
  ┌─────┬─────┬─────┬─────┬─────┬─────┐
  │  A  │  B  │ D0  │ D1  │ D2  │ D3  │
  ├─────┼─────┼─────┼─────┼─────┼─────┤
  │  0  │  0  │  1  │  0  │  0  │  0  │
  │  0  │  1  │  0  │  1  │  0  │  0  │
  │  1  │  0  │  0  │  0  │  1  │  0  │
  │  1  │  1  │  0  │  0  │  0  │  1  │
  └─────┴─────┴─────┴─────┴─────┴─────┘

2.5 Encoder (4:2 Priority Encoder)

The reverse of a decoder. Takes 2ⁿ input lines and produces an n-bit binary code. A priority encoder handles the case when multiple inputs are active — it encodes the highest-priority one.

  4:2 PRIORITY ENCODER — Truth Table
  ┌─────┬─────┬─────┬─────┬─────┬─────┬───────┐
  │ I3  │ I2  │ I1  │ I0  │  A  │  B  │ Valid │
  ├─────┼─────┼─────┼─────┼─────┼─────┼───────┤
  │  0  │  0  │  0  │  0  │  X  │  X  │   0   │
  │  0  │  0  │  0  │  1  │  0  │  0  │   1   │
  │  0  │  0  │  1  │  X  │  0  │  1  │   1   │
  │  0  │  1  │  X  │  X  │  1  │  0  │   1   │
  │  1  │  X  │  X  │  X  │  1  │  1  │   1   │
  └─────┴─────┴─────┴─────┴─────┴─────┴───────┘
  (X = Don't Care — higher priority input overrides lower)

2.6 Ripple Carry Adder (4-bit)

Four Full Adders cascaded — the carry-out of each stage "ripples" into the carry-in of the next. This adds two 4-bit binary numbers.

  4-BIT RIPPLE CARRY ADDER

   A3 B3        A2 B2        A1 B1        A0 B0
    │  │         │  │         │  │         │  │
    ▼  ▼         ▼  ▼         ▼  ▼         ▼  ▼
  ┌──────┐     ┌──────┐     ┌──────┐     ┌──────┐
  │      │     │      │     │      │     │      │
  │  FA  │◄────│  FA  │◄────│  FA  │◄────│  FA  │◄── C0 (0)
  │  3   │ C3  │  2   │ C2  │  1   │ C1  │  0   │
  │      │     │      │     │      │     │      │
  └──┬───┘     └──┬───┘     └──┬───┘     └──┬───┘
     │            │            │            │
  C4(Cout)       S3           S2           S1          S0

  Example: A = 0101 (5), B = 0011 (3), Cin = 0
  ─────────────────────────────────────────────────
  FA0: A0=1, B0=1, Cin=0 → S0=0, C1=1
  FA1: A1=0, B1=1, Cin=1 → S1=0, C2=1
  FA2: A2=1, B2=0, Cin=1 → S2=0, C3=1
  FA3: A3=0, B3=0, Cin=1 → S3=1, C4=0
  Result: S = 1000 (8) ✓  (5 + 3 = 8)

Students forget that carry ripples cause delay. In a 4-bit RCA, the worst-case delay is 4 × (gate delay per FA). For a 64-bit adder, this becomes unacceptably slow. That's why real processors use Carry Look-Ahead Adders (CLA) that compute all carries in parallel using generate (G) and propagate (P) signals.

The ALU inside your phone's processor doesn't use Ripple Carry Adders. Modern ARM processors (used in Qualcomm Snapdragon chips designed partly in Hyderabad) use Carry Look-Ahead and Carry-Select Adder hybrids that complete 64-bit addition in under 1 nanosecond.

3. Sequential Circuits — Circuits with Memory

Definition: A sequential circuit's output depends on both current inputs AND past history (stored state). It has feedback loops and is typically controlled by a clock signal.

Analogy — The ATM Machine: A sequential circuit is like an ATM. It remembers your state — "Card inserted? PIN entered? Amount selected?" Each action moves it to the next state. The ATM's output (dispense cash, show error) depends on its current state AND your current input. It has memory — it knows where you are in the process.

Feature	Combinational Circuit	Sequential Circuit
Memory	❌ No memory	✅ Has memory (flip-flops)
Feedback	❌ No feedback path	✅ Output fed back to input
Clock	❌ Not needed	✅ Clock-driven (synchronous)
Output depends on	Current inputs only	Current inputs + present state
Examples	Adder, MUX, Decoder, Encoder	Flip-flops, Counters, Registers
ISRO PSLV use	Thrust calculations	Flight state tracking

3.1 SR Flip-Flop (Set-Reset)

The most basic memory element. Has two inputs: S (Set) and R (Reset). Stores one bit of data.

  SR FLIP-FLOP — Truth Table
  ┌─────┬─────┬────────┬──────────────────────┐
  │  S  │  R  │  Q(t+1)│     Action           │
  ├─────┼─────┼────────┼──────────────────────┤
  │  0  │  0  │  Q(t)  │  No change (Hold)    │
  │  0  │  1  │   0    │  Reset               │
  │  1  │  0  │   1    │  Set                 │
  │  1  │  1  │   ?    │  ⚠ INVALID (Race!)   │
  └─────┴─────┴────────┴──────────────────────┘

  Characteristic Equation: Q(t+1) = S + R'·Q(t)
  Constraint: S·R = 0  (S and R cannot both be 1)

  ┌────────────────────────────────────┐
  │         SR FLIP-FLOP               │
  │                                    │
  │  S ────►┌──────┐                   │
  │         │  NOR ├──► Q              │
  │    ┌───►│      │     │             │
  │    │    └──────┘     │             │
  │    │                 │(Feedback)   │
  │    │    ┌──────┐     │             │
  │    └────┤  NOR │◄────┘             │
  │         │      ├──► Q'             │
  │  R ────►│      │                   │
  │         └──────┘                   │
  └────────────────────────────────────┘

S=1, R=1 is FORBIDDEN in an SR flip-flop. It forces both Q and Q' to 0, violating the rule Q' = complement of Q. When both S and R return to 0, the output is unpredictable (race condition). This is the fundamental limitation that led to the invention of JK and D flip-flops.

3.2 D Flip-Flop (Data/Delay)

Solves the SR flip-flop's invalid state problem by using a single data input. Whatever is on D at the clock edge gets stored. Think of it as a "copy-paste on clock tick" circuit.

  D FLIP-FLOP — Truth Table
  ┌─────┬────────┬──────────────────────┐
  │  D  │ Q(t+1) │     Action           │
  ├─────┼────────┼──────────────────────┤
  │  0  │   0    │  Stores 0 (Reset)    │
  │  1  │   1    │  Stores 1 (Set)      │
  └─────┴────────┴──────────────────────┘

  Characteristic Equation: Q(t+1) = D
  (Output simply follows input at each clock edge)

  ┌──────────────────────────┐
  │      D FLIP-FLOP         │
  │                          │
  │  D ──────►┌─────┐        │
  │           │     │──► Q   │
  │  CLK ────►│  D  │        │
  │           │  FF │──► Q'  │
  │           └─────┘        │
  └──────────────────────────┘

3.3 JK Flip-Flop (The Universal Flip-Flop)

The most versatile flip-flop. Fixes the SR flip-flop's invalid state — when J=1, K=1, the output toggles (flips to opposite). Named after Jack Kilby, inventor of the integrated circuit.

  JK FLIP-FLOP — Truth Table
  ┌─────┬─────┬────────┬──────────────────────┐
  │  J  │  K  │ Q(t+1) │     Action           │
  ├─────┼─────┼────────┼──────────────────────┤
  │  0  │  0  │  Q(t)  │  No change (Hold)    │
  │  0  │  1  │   0    │  Reset               │
  │  1  │  0  │   1    │  Set                 │
  │  1  │  1  │  Q'(t) │  Toggle              │
  └─────┴─────┴────────┴──────────────────────┘

  Characteristic Equation: Q(t+1) = J·Q'(t) + K'·Q(t)

GATE Trick: Any flip-flop can be converted to any other. To convert JK → D: Connect D to J and D' to K. To convert JK → T: Connect J = K = T. These conversions are asked in GATE almost every other year.

3.4 T Flip-Flop (Toggle)

A simplified JK flip-flop with a single input T. When T=1, the output toggles on every clock edge. Perfect for building binary counters.

  T FLIP-FLOP — Truth Table
  ┌─────┬────────┬──────────────────────┐
  │  T  │ Q(t+1) │     Action           │
  ├─────┼────────┼──────────────────────┤
  │  0  │  Q(t)  │  No change (Hold)    │
  │  1  │  Q'(t) │  Toggle              │
  └─────┴────────┴──────────────────────┘

  Characteristic Equation: Q(t+1) = T ⊕ Q(t)
  (T=1: flip; T=0: hold)

3.5 Flip-Flop Comparison Table

Feature	SR	D	JK	T
Inputs	S, R	D	J, K	T
Invalid state?	Yes (S=R=1)	No	No	No
Toggle?	No	No	Yes (J=K=1)	Yes (T=1)
Char. Equation	S + R'Q	D	JQ' + K'Q	T ⊕ Q
Best for	Basic latch	Registers, data storage	Counters, universal use	Frequency dividers
GATE frequency	Low	High	Very High	Medium

3.6 4-Bit Register

A register is a group of flip-flops that stores a multi-bit binary word. A 4-bit register uses 4 D flip-flops, all sharing the same clock, to store a 4-bit value.

  4-BIT PARALLEL REGISTER (using D Flip-Flops)

  D3─►┌────┐   D2─►┌────┐   D1─►┌────┐   D0─►┌────┐
      │ D  │       │ D  │       │ D  │       │ D  │
      │ FF │       │ FF │       │ FF │       │ FF │
      │    │       │    │       │    │       │    │
  CLK►│    │   CLK►│    │   CLK►│    │   CLK►│    │
      └─┬──┘       └─┬──┘       └─┬──┘       └─┬──┘
        │             │            │            │
       Q3            Q2           Q1           Q0

  ════════════════════════════════════════════
  CLK ──────────┘  └──────────┘  └──────────┘
  (Common clock — all FFs sample D simultaneously)

  On each rising clock edge:
    Q3←D3, Q2←D2, Q1←D1, Q0←D0

  Example: Load value 1010
  Set D3=1, D2=0, D1=1, D0=0 → on clock edge → Q = 1010

3.7 3-Bit Asynchronous (Ripple) Counter

A counter that counts in binary from 000 to 111 (0 to 7) and then wraps around. Uses T flip-flops with T=1 (always toggle). Each flip-flop's output clocks the next one.

  3-BIT RIPPLE COUNTER (using T Flip-Flops, T=1)

                    ┌──────┐      ┌──────┐      ┌──────┐
  CLK ────────────►│ T FF │────►│ T FF │────►│ T FF │
                    │  Q0  │ Q0  │  Q1  │ Q1  │  Q2  │
                    │(LSB) │clock│      │clock│(MSB) │
                    └──┬───┘      └──┬───┘      └──┬───┘
                       │             │              │
                      Q0            Q1             Q2

  State Sequence (Count-Up):
  ┌───────┬─────┬─────┬─────┬─────────┐
  │ Clock │ Q2  │ Q1  │ Q0  │ Decimal │
  ├───────┼─────┼─────┼─────┼─────────┤
  │   0   │  0  │  0  │  0  │    0    │
  │   1   │  0  │  0  │  1  │    1    │
  │   2   │  0  │  1  │  0  │    2    │
  │   3   │  0  │  1  │  1  │    3    │
  │   4   │  1  │  0  │  0  │    4    │
  │   5   │  1  │  0  │  1  │    5    │
  │   6   │  1  │  1  │  0  │    6    │
  │   7   │  1  │  1  │  1  │    7    │
  │   8   │  0  │  0  │  0  │  0 (↺)  │
  └───────┴─────┴─────┴─────┴─────────┘
  Counts from 0 to 2³−1 = 7, then resets to 0.
  Modulus = 2³ = 8 (Mod-8 counter)

ISRO's onboard timer uses sequential counters to track mission elapsed time. A 32-bit counter at 10 MHz clock can count up to 2³² − 1 = 4,294,967,295 clock ticks, which equals ~429 seconds (~7 minutes). For the full PSLV mission (~20 minutes to orbit), they use cascaded counters with wider bit-widths.

Section D

Learn by Doing — 3-Tier Lab Structure

🟢 Tier 1 — GUIDED: Truth Table Trace for Full Adder

⏱️ 30–45 minutesBeginnerPen-and-paper exercise

Objective:

Manually trace the truth table of a Full Adder and verify the Sum and Carry-Out equations gate by gate.

Step 1: Draw the Circuit

Draw a Full Adder using 2 XOR gates, 2 AND gates, and 1 OR gate. Label all intermediate wires.

  A ─────┬───►[XOR1]───P──┬───►[XOR2]─────► Sum
         │                │       ▲
  B ─────┼───►           │      │
         │    [AND1]──G   │   Cin─┤
         │       ▲        │      │
         │       │        ├───►[AND2]──T
         │       B        │
         A                │
                          │    ┌──────┐
                     G───►│───►│      │
                          │    │  OR  ├───► Cout
                     T───►│───►│      │
                               └──────┘

  Where: P = A ⊕ B,  G = A·B,  T = P·Cin

Step 2: Trace Row by Row

For each input combination, compute every intermediate signal:

A	B	Cin	P=A⊕B	G=A·B	T=P·Cin	Sum=P⊕Cin	Cout=G+T
0	0	0	0	0	0	0	0
0	0	1	0	0	0	1	0
0	1	0	1	0	0	1	0
0	1	1	1	0	1	0	1
1	0	0	1	0	0	1	0
1	0	1	1	0	1	0	1
1	1	0	0	1	0	0	1
1	1	1	0	1	0	1	1

Step 3: Verify

Check that Sum = A ⊕ B ⊕ Cin and Cout = AB + Cin(A ⊕ B) match for every row. If even one row doesn't match, your wiring has a bug — go back and trace again.

Stretch Goal: Now trace a Half Subtractor. Inputs: A, B. Outputs: Difference = A ⊕ B, Borrow = A'·B. Draw its truth table and gate diagram.

🟡 Tier 2 — SEMI-GUIDED: Build a 4-Bit Ripple Carry Adder on Paper

⏱️ 60–90 minutesIntermediateCircuit design + numerical verification

Your Mission:

Design a 4-bit Ripple Carry Adder, then use it to compute 3 additions manually.

Tasks:

Draw the full circuit: 4 Full Adders cascaded, with carry chain clearly shown
Compute: 7 + 5 = ? (0111 + 0101). Trace carry through each FA stage.
Compute: 9 + 6 = ? (1001 + 0110). Does it overflow for 4 bits?
Compute: 15 + 1 = ? (1111 + 0001). What happens? Explain overflow.
Calculate worst-case propagation delay if each FA has a delay of 10 ns.

Expected Results:

Operation	Binary A	Binary B	Result	Carry Out	Overflow?
7 + 5	0111	0101	1100 (12)	0	No
9 + 6	1001	0110	1111 (15)	0	No
15 + 1	1111	0001	0000 (0!)	1	Yes!

Worst-case delay for n-bit RCA = 2n × gate_delay. Each FA has 2 gate levels for carry. For 4-bit RCA with 10 ns gate delay: worst case = 2 × 4 × 10 = 80 ns. A 64-bit RCA would take 1280 ns — far too slow for GHz processors!

🔴 Tier 3 — OPEN CHALLENGE: Python Truth Table Generator

⏱️ 90–120 minutesAdvancedPython programming project

The Brief:

Write a Python program that generates truth tables for any n-input combinational circuit. The user provides a Boolean expression, and the program outputs the complete truth table.

Python
# Truth Table Generator for Combinational Circuits
from itertools import product

def generate_truth_table(variables, expression):
    """Generate truth table for a Boolean expression."""
    n = len(variables)
    
    # Print header
    header = " | ".join(variables) + " | Output"
    print(header)
    print("-" * len(header))
    
    # Generate all input combinations
    for values in product([0, 1], repeat=n):
        # Map variable names to values
        env = dict(zip(variables, values))
        
        # Evaluate expression
        result = eval(expression, {"__builtins__": {}}, env)
        result = 1 if result else 0
        
        row = " | ".join(str(v) for v in values)
        print(f"{row} |   {result}")

# Example: Full Adder
print("=== FULL ADDER: Sum ===")
generate_truth_table(
    ["A", "B", "C"],
    "(A ^ B ^ C)"   # XOR for Sum
)

print("\n=== FULL ADDER: Carry ===")
generate_truth_table(
    ["A", "B", "C"],
    "(A and B) or (C and (A ^ B))"  # Carry equation
)

print("\n=== 2:4 DECODER ===")
for i in range(4):
    print(f"\nOutput D{i}:")
    expr = [
        "(not A) and (not B)",
        "(not A) and B",
        "A and (not B)",
        "A and B"
    ][i]
    generate_truth_table(["A", "B"], expr)

=== FULL ADDER: Sum === A | B | C | Output -------------------- 0 | 0 | 0 | 0 0 | 0 | 1 | 1 0 | 1 | 0 | 1 0 | 1 | 1 | 0 1 | 0 | 0 | 1 1 | 0 | 1 | 0 1 | 1 | 0 | 0 1 | 1 | 1 | 1

Stretch Goals:
• Add a 4:1 MUX simulation that accepts select lines + data inputs
• Add a JK flip-flop simulator that takes a clock sequence and shows Q at each edge
• Output truth tables as formatted HTML files (portfolio piece!)

Section E

Problem Bank — Diagrams, Numericals, Industry & GATE

Diagram-Based Problems (3)

📐 P1: Draw the gate-level circuit for a 4:1 MUX using basic gates

Task: Using AND, OR, and NOT gates only, draw the complete circuit for a 4:1 MUX with inputs I0–I3, select lines S1, S0, and output Y.

Solution:

  S1 ──┬──►[NOT]──S1'    S0 ──┬──►[NOT]──S0'
       │                       │
       │                       │
  I0 ──►[AND]◄── S1' ◄── S0'  ──► AND0 out
  I1 ──►[AND]◄── S1' ◄── S0   ──► AND1 out
  I2 ──►[AND]◄── S1  ◄── S0'  ──► AND2 out      ──►[OR]──► Y
  I3 ──►[AND]◄── S1  ◄── S0   ──► AND3 out

  Each AND gate is 3-input:
  AND0 = I0 · S1' · S0'
  AND1 = I1 · S1' · S0
  AND2 = I2 · S1  · S0'
  AND3 = I3 · S1  · S0
  Y    = AND0 + AND1 + AND2 + AND3

Gate count: 2 NOT + 4 AND (3-input) + 1 OR (4-input) = 7 gates total.

📐 P2: Draw a 3-bit synchronous counter using JK flip-flops

Task: Design a Mod-8 synchronous up-counter. All flip-flops share the same clock. Show the excitation table and connections.

Solution:

  Excitation Table (JK FF):
  ┌────────┬────────┬─────────────────────────────┐
  │Present │  Next  │  JK inputs needed           │
  │Q2 Q1 Q0│Q2 Q1 Q0│  J2 K2  J1 K1  J0 K0       │
  ├────────┼────────┼─────────────────────────────┤
  │ 0  0  0│ 0  0  1│  0  X   0  X   1  X        │
  │ 0  0  1│ 0  1  0│  0  X   1  X   X  1        │
  │ 0  1  0│ 0  1  1│  0  X   X  0   1  X        │
  │ 0  1  1│ 1  0  0│  1  X   X  1   X  1        │
  │ 1  0  0│ 1  0  1│  X  0   0  X   1  X        │
  │ 1  0  1│ 1  1  0│  X  0   1  X   X  1        │
  │ 1  1  0│ 1  1  1│  X  0   X  0   1  X        │
  │ 1  1  1│ 0  0  0│  X  1   X  1   X  1        │
  └────────┴────────┴─────────────────────────────┘

  Simplified (using K-maps):
  J0 = K0 = 1  (always toggle)
  J1 = K1 = Q0
  J2 = K2 = Q0 · Q1

  Circuit:
          ┌──────┐       ┌──────┐       ┌──────┐
  1 ──J0─►│ JK   │  Q0─J1►│ JK   │Q0·Q1─J2►│ JK   │
  1 ──K0─►│ FF0  │  Q0─K1►│ FF1  │Q0·Q1─K2►│ FF1  │
  CLK────►│      │  CLK──►│      │  CLK───►│      │
          └──┬───┘        └──┬───┘         └──┬───┘
            Q0              Q1                Q2

📐 P3: Draw the timing diagram for a D flip-flop

Task: Given CLK and D waveforms, draw Q output for a positive-edge-triggered D flip-flop.

  CLK:  ──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──
          └──┘  └──┘  └──┘  └──┘  └──┘  └──┘
  Edge:    ↑1    ↑2    ↑3    ↑4    ↑5    ↑6
          
  D:    ──1──1──0──0──1──1──0──0──1──1──0──0──
  
  Q:    ──0──1──1──0──0──1──1──0──0──1──1──0──
           ↑     ↑     ↑     ↑     ↑     ↑
           D=1   D=0   D=1   D=0   D=1   D=0
           at↑1  at↑2  at↑3  at↑4  at↑5  at↑6

  Rule: Q takes the value of D at each rising edge of CLK.
  Between clock edges, Q holds its previous value.

Numerical Problems (6)

🔢 N1: Binary Addition using 4-bit RCA

Q: Add 1011₂ (11) and 0110₂ (6) using a 4-bit Ripple Carry Adder. Show carry at each stage.

Solution:

  FA0: A0=1, B0=0, Cin=0 → Sum=1, Cout=0
  FA1: A1=1, B1=1, Cin=0 → Sum=0, Cout=1
  FA2: A2=0, B2=1, Cin=1 → Sum=0, Cout=1
  FA3: A3=1, B3=0, Cin=1 → Sum=0, Cout=1
  
  Result: Cout=1, S = 0001
  Full answer: 10001₂ = 17₁₀  ✓ (11 + 6 = 17)
  Note: Cout=1 means result needs 5 bits.

🔢 N2: MUX-based Function Implementation

Q: Implement f(A,B) = Σm(1,2,3) using a 4:1 MUX.

Solution:

  Truth table:
  A  B | f
  0  0 | 0  → I0 = 0
  0  1 | 1  → I1 = 1
  1  0 | 1  → I2 = 1
  1  1 | 1  → I3 = 1

  Connect: S1=A, S0=B
  I0=0 (GND), I1=1 (VCC), I2=1 (VCC), I3=1 (VCC)
  
  This is equivalent to f = A + B (OR gate)

🔢 N3: Propagation Delay Calculation

Q: A 16-bit Ripple Carry Adder uses Full Adders with a gate delay of 5 ns per gate. Each FA has 2 gate levels for carry propagation. Calculate the worst-case delay.

Solution:

  Worst-case carry delay per FA = 2 × 5 ns = 10 ns
  Total carry chain for 16-bit = 16 FAs
  Worst-case total delay = 16 × 10 ns = 160 ns
  
  Maximum operating frequency = 1 / 160 ns = 6.25 MHz
  
  Compare: Modern CPUs run at 4 GHz = 0.25 ns per cycle
  This is why RCA is NOT used in real processors!

🔢 N4: Flip-Flop State Sequence

Q: A JK flip-flop has J=1, K=1 with initial Q=0. What is Q after 5 clock pulses?

Solution:

  J=K=1 → Toggle mode
  
  Initial: Q = 0
  After clock 1: Q = 1 (toggled)
  After clock 2: Q = 0 (toggled)
  After clock 3: Q = 1 (toggled)
  After clock 4: Q = 0 (toggled)
  After clock 5: Q = 1 (toggled)
  
  Answer: Q = 1 after 5 clock pulses.
  Pattern: Q toggles every clock → acts as frequency divider ÷2

🔢 N5: Counter Modulus

Q: How many flip-flops are needed for a Mod-12 counter? What is the maximum count?

Solution:

  Need to count 12 states: 0 to 11
  
  Number of FFs = ⌈log₂(12)⌉ = ⌈3.585⌉ = 4 flip-flops
  
  4 FFs can count 0 to 15 (Mod-16 naturally)
  For Mod-12: Reset to 0 when count reaches 12 (1100₂)
  Maximum valid count = 11 (1011₂)
  
  Reset logic: When Q3=1, Q2=1, Q1=0, Q0=0 → CLEAR all FFs
  Reset = Q3 · Q2 (since 12 = 1100, we detect this and reset)

🔢 N6: Decoder Output Minterms

Q: A 3:8 decoder has inputs A₂A₁A₀ = 101. Which output line is active?

Solution:

  Input: A₂=1, A₁=0, A₀=1
  Binary 101 = Decimal 5
  
  Output D5 is active (HIGH), all others are LOW.
  
  D5 = A₂ · A₁' · A₀ = 1 · 1 · 1 = 1 ✓
  
  A 3:8 decoder generates all 8 minterms of 3 variables.
  This is why decoders can implement ANY Boolean function
  by OR-ing the appropriate output lines.

Industry Application Problems (3)

🏭 I1: ISRO Flight Computer — Stage Separation Logic

Scenario: PSLV has 4 stages. The flight computer must activate stage separation only when: (1) current stage fuel is depleted (F=1), (2) altitude is above minimum threshold (A=1), AND (3) separation command is received from ground or timer (C=1).

Task: Design the combinational logic circuit for the SEPARATE signal.

  SEPARATE = F · A · C  (3-input AND gate)
  
  Truth Table:
  F  A  C | SEPARATE
  0  0  0 |    0     (fuel remaining, don't separate)
  0  0  1 |    0
  0  1  0 |    0
  0  1  1 |    0
  1  0  0 |    0     (fuel done but too low altitude!)
  1  0  1 |    0
  1  1  0 |    0     (fuel done, altitude OK, no command)
  1  1  1 |    1     ✅ SEPARATE NOW!
  
  Safety: Only 1 out of 8 conditions triggers separation.
  This is intentional — fail-safe design.

🏭 I2: Qualcomm Hyderabad — Power Management MUX

Scenario: A Snapdragon SoC has 4 power modes: Active (00), Idle (01), Sleep (10), Deep Sleep (11). A 4:1 MUX selects the appropriate clock frequency based on the power mode.

Task: Design the MUX configuration.

  Power Mode Select Lines: S1, S0
  Clock frequencies (input to MUX):
    I0 = 2.4 GHz  (Active — full speed)
    I1 = 800 MHz   (Idle — reduced)
    I2 = 100 MHz   (Sleep — minimal)
    I3 = 32 KHz    (Deep Sleep — near zero)
  
  Output Y = selected clock frequency
  
  This is exactly how modern phone chipsets save battery.
  When you lock your phone, S1S0 transitions from 00→01→10→11
  reducing power consumption by 99%.

🏭 I3: Indian Railways — Signal Interlocking Logic

Scenario: At a junction, two train routes (R1, R2) must never be green simultaneously. Design a combinational circuit that ensures safety interlocking.

  Inputs: Request_R1, Request_R2
  Outputs: Green_R1, Green_R2

  Safety Rule: Green_R1 · Green_R2 = 0 (NEVER both green)

  Logic:
  Green_R1 = Request_R1 · Request_R2'  (R1 only if R2 not requested)
  Green_R2 = Request_R2 · Request_R1'  (R2 only if R1 not requested)
  
  If both requested simultaneously:
  Green_R1 = 0, Green_R2 = 0 (BOTH RED — safe default)
  
  Additional priority logic can be added to handle conflicts.
  Indian Railways uses similar relay-based interlocking at 7,000+ stations.

GATE-Style Problems (5)

🎯 GATE Q1 [1 Mark]

Q: The number of 2-input AND and OR gates required to implement the Boolean function F(A,B,C) = AB + BC + CA in Sum-of-Products form is:

3 AND, 1 OR
3 AND, 3 OR
2 AND, 1 OR
3 AND, 2 OR

Answer: (A) — F = AB + BC + CA has 3 product terms (3 AND gates) combined by 1 OR gate. But the OR gate needs 3 inputs. Using 2-input OR gates: need 2 OR gates (cascade). So strictly: 3 AND + 2 OR. Answer is (A) if 3-input OR is allowed, (D) if only 2-input. GATE usually allows multi-input gates.

🎯 GATE Q2 [2 Marks]

Q: A 4-bit ripple carry adder adds two 4-bit numbers. The gate delay is Δ per gate. What is the worst-case delay for the carry output of the MSB stage?

4Δ
8Δ
12Δ
16Δ

Answer: (B) 8Δ — Each Full Adder has 2 gate levels for carry propagation (AND + OR). For 4 stages: 4 × 2Δ = 8Δ. Note: First FA carry takes 2Δ, and each subsequent FA adds 2Δ to the carry chain.

🎯 GATE Q3 [1 Mark]

Q: The characteristic equation of a JK flip-flop is:

Q(t+1) = JQ + K'Q'
Q(t+1) = JQ' + K'Q
Q(t+1) = J'Q + KQ'
Q(t+1) = J ⊕ Q

Answer: (B) — Q(t+1) = J·Q'(t) + K'·Q(t). Verify: J=0,K=0 → Q(hold) ✓; J=0,K=1 → 0(reset) ✓; J=1,K=0 → 1(set) ✓; J=1,K=1 → Q'(toggle) ✓.

🎯 GATE Q4 [2 Marks]

Q: An 8:1 MUX is used to implement a 3-variable Boolean function f(A,B,C). A, B, C are connected to S2, S1, S0 respectively. For f = Σm(1,2,4,7), the values of I0 through I7 are:

0,1,1,0,1,0,0,1
1,1,0,1,0,0,1,0
0,1,1,0,0,1,0,1
1,0,0,1,1,0,1,0

Answer: (A) — f = Σm(1,2,4,7). Minterms present: m1, m2, m4, m7. So I1=1, I2=1, I4=1, I7=1; rest = 0. Sequence: I0=0, I1=1, I2=1, I3=0, I4=1, I5=0, I6=0, I7=1.

🎯 GATE Q5 [2 Marks]

Q: A 3-bit synchronous counter using JK flip-flops counts the sequence: 0→1→2→3→4→5→6→7→0. The flip-flop inputs for the MSB (Q2) are:

J2 = Q1·Q0, K2 = Q1·Q0
J2 = Q1+Q0, K2 = Q1+Q0
J2 = Q1⊕Q0, K2 = 1
J2 = 1, K2 = 1

Answer: (A) — From the excitation table, Q2 transitions 0→1 only when Q1=Q0=1 (count 3→4), and 1→0 only when Q1=Q0=1 (count 7→0). So J2 = K2 = Q1·Q0.

Section F

MCQ Assessment Bank — 30 Questions (Bloom's Mapped)

Remember / Identify (Q1–Q5)

Which unit of a computer performs arithmetic and logical operations?

Control Unit
Memory Unit
ALU
Input Unit

Remember

✅ Answer: (C) ALU — The Arithmetic Logic Unit performs all arithmetic (+, −, ×, ÷) and logical (AND, OR, NOT) operations.

The output of a Half Adder for inputs A=1, B=1 is:

Sum=1, Carry=0
Sum=0, Carry=1
Sum=1, Carry=1
Sum=0, Carry=0

Remember

✅ Answer: (B) — Sum = 1⊕1 = 0, Carry = 1·1 = 1. In binary: 1+1 = 10 (sum=0, carry=1).

How many select lines does an 8:1 MUX have?

Remember

✅ Answer: (B) 3 — An 8:1 MUX needs log₂(8) = 3 select lines to choose one of 8 inputs.

The characteristic equation of a D flip-flop is:

Q(t+1) = D
Q(t+1) = D ⊕ Q
Q(t+1) = D·Q'
Q(t+1) = D + Q

Remember

✅ Answer: (A) Q(t+1) = D — The D flip-flop simply copies the input D to output Q on each clock edge.

A 2:4 decoder has how many output lines?

Remember

✅ Answer: (B) 4 — A 2:4 decoder has 2 input lines and 2² = 4 output lines.

Understand / Explain (Q6–Q10)

Why is the S=1, R=1 condition invalid in an SR flip-flop?

It consumes too much power
It forces Q and Q' to both be 0, violating the complement rule
It damages the circuit physically
It causes the clock to stop

Understand

✅ Answer: (B) — When S=R=1, both NOR gates output 0, so Q=Q'=0. This violates the fundamental rule that Q' must be the complement of Q. The state becomes unpredictable when inputs return to 0.

In a 4-bit Ripple Carry Adder, why does the MSB stage produce the result last?

It has more gates
It must wait for the carry to ripple through all previous stages
The MSB is always the slowest bit
It uses a different clock

Understand

✅ Answer: (B) — The carry out of each stage is the carry in for the next. FA3 cannot compute its result until it receives C3 from FA2, which waits for C2 from FA1, which waits for C1 from FA0. This "ripple" causes increasing delay.

What does it mean when we say a MUX is a "universal logic element"?

It can replace any power supply
It can implement any Boolean function without other gates
It works at any frequency
It can store data like a flip-flop

Understand

✅ Answer: (B) — A 2ⁿ:1 MUX can implement any n-variable Boolean function by connecting the function's truth table output values to the MUX data inputs and the variables to the select lines.

How does a sequential circuit differ from a combinational circuit fundamentally?

Sequential circuits are faster
Sequential circuits have memory elements (feedback) while combinational don't
Sequential circuits don't use logic gates
Combinational circuits require a clock

Understand

✅ Answer: (B) — The key difference is memory. Sequential circuits have feedback paths and flip-flops that store state. Their output depends on current input AND past history. Combinational outputs depend only on current inputs.

Q10

Why is the D flip-flop preferred over SR flip-flop for data storage registers?

It's cheaper
It has no invalid state and directly stores whatever value is on its input
It runs at higher frequency
It uses fewer transistors

Understand

✅ Answer: (B) — The D flip-flop eliminates the invalid S=R=1 condition entirely (since there's only one data input). Q(t+1) = D — clean, predictable, no race conditions. This is why it's universally used in registers and data storage.

Apply / Solve (Q11–Q15)

Q11

A Full Adder has inputs A=1, B=0, Cin=1. The outputs Sum and Cout are:

Sum=0, Cout=1
Sum=1, Cout=1
Sum=0, Cout=0
Sum=1, Cout=0

Apply

✅ Answer: (A) — Sum = 1⊕0⊕1 = 0. Cout = (1·0) + (1·(1⊕0)) = 0 + 1·1 = 1. Verification: 1+0+1 = 10₂ (Sum=0, Carry=1) ✓

Q12

In a 4:1 MUX with S1=1, S0=0, which input is selected?

Apply

✅ Answer: (C) I2 — S1S0 = 10₂ = 2₁₀. So input I2 is selected and passed to the output.

Q13

A JK flip-flop with J=1, K=0 and current Q=0. After one clock pulse, Q becomes:

0
1
Toggles
Undefined

Apply

✅ Answer: (B) 1 — J=1, K=0 → Set operation. Q(t+1) = 1 regardless of current Q. Using characteristic equation: Q(t+1) = J·Q' + K'·Q = 1·1 + 1·0 = 1.

Q14

How many Full Adders are needed to build a 16-bit adder?

Apply

✅ Answer: (C) 16 — Each bit position needs one Full Adder. For n-bit addition, we need n Full Adders in a Ripple Carry configuration (the LSB could use a Half Adder if Cin=0, but typically we use 16 FAs).

Q15

A 3:8 decoder with inputs A₂A₁A₀ = 011. Which output is HIGH?

Apply

✅ Answer: (B) D3 — 011₂ = 3₁₀. So output line D3 is active (HIGH), all others LOW.

Analyze / Compare (Q16–Q20)

Q16

A Carry Look-Ahead Adder is faster than a Ripple Carry Adder because:

It uses fewer gates
It computes all carry bits simultaneously using generate and propagate logic
It doesn't need carry bits
It uses sequential logic instead of combinational

Analyze

✅ Answer: (B) — CLA pre-computes carries using Generate (Gi = Ai·Bi) and Propagate (Pi = Ai⊕Bi) signals. All carries are computed in O(1) gate levels instead of O(n) for RCA, making it dramatically faster for wide adders.

Q17

Which flip-flop type can be used to implement all other flip-flop types?

Analyze

✅ Answer: (C) JK — The JK flip-flop is called the "universal" flip-flop. JK→D: Connect J=D, K=D'. JK→T: Connect J=K=T. JK→SR: Connect J=S, K=R. No other flip-flop can convert to all others this easily.

Q18

In a ripple counter vs. a synchronous counter, the primary disadvantage of the ripple counter is:

Uses more flip-flops
Higher power consumption
Cumulative propagation delay due to asynchronous clocking
Cannot count beyond 8

Analyze

✅ Answer: (C) — In a ripple counter, each FF clocks the next, causing cumulative delay. For n bits: total delay = n × FF propagation delay. In synchronous counters, all FFs share the same clock, so delay is constant regardless of bit count.

Q19

A decoder can be used as a demultiplexer if:

Output lines are grounded
An enable input is used as the data line
Extra flip-flops are added
Clock is connected to inputs

Analyze

✅ Answer: (B) — A decoder with enable acts as a DEMUX. The address lines select which output receives the data (enable line). When Enable=1, the selected output is 1; when Enable=0, the selected output is 0. This routes the enable signal to one of 2ⁿ outputs.

Q20

Which combination correctly identifies memory elements?

MUX and Decoder — both have memory
Flip-flop and Register — both have memory
Adder and Encoder — both have memory
Counter and MUX — both have memory

Analyze

✅ Answer: (B) — Flip-flops store 1 bit, Registers store n bits (group of flip-flops). MUX, Decoder, Adder, and Encoder are all combinational (no memory). Counter has memory (sequential).

Evaluate / Justify (Q21–Q25)

Q21

For a frequency divider circuit, which flip-flop configuration is most appropriate?

SR with S=R=0
D with D connected to Q'
JK with J=K=1
Both (B) and (C)

Evaluate

✅ Answer: (D) — Both configurations create a toggle (divide-by-2). D FF with D=Q': Q toggles every clock. JK with J=K=1: Q toggles every clock. Both divide input frequency by 2. Either is valid for frequency dividers.

Q22

A 4-bit register can be built using which of the following?

4 AND gates
4 D flip-flops with common clock
4 MUX circuits
4 decoders

Evaluate

✅ Answer: (B) — A register stores data, requiring memory elements. D flip-flops with a common clock simultaneously capture 4 bits on each clock edge. AND gates, MUX, and decoders are combinational and cannot store data.

Q23

If a circuit has both combinational and sequential parts, it is classified as:

Combinational
Sequential
Hybrid only
Neither

Evaluate

✅ Answer: (B) Sequential — Any circuit with memory/feedback is sequential, even if it also contains combinational logic. A counter, for example, has combinational logic (excitation logic) feeding sequential elements (flip-flops).

Q24

For implementing Boolean function f(A,B,C) = Σm(0,3,5,6), which is more gate-efficient?

Using discrete AND-OR gates (SOP form)
Using an 8:1 MUX
Both use equal gates
Cannot be determined

Evaluate

✅ Answer: (B) — The SOP form requires simplification via K-map and may need 3-4 AND gates + 1 OR gate + inverters. An 8:1 MUX needs just 1 IC (no additional gates) — connect S2=A, S1=B, S0=C and tie I0,I3,I5,I6 to 1, rest to 0. The MUX approach is simpler and more systematic.

Q25

In PSLV's flight computer, why would sequential circuits be preferred over combinational circuits for tracking the rocket's flight phase?

Sequential circuits are cheaper
Flight phases depend on history/state, which only sequential circuits can track
Combinational circuits cannot perform arithmetic
Sequential circuits are always faster

Evaluate

✅ Answer: (B) — The rocket's current phase (Stage 1 burn, Stage 1 separation, Stage 2 ignition, etc.) depends on the sequence of events that have already occurred. Only sequential circuits can remember "what state we're in" and transition to the next state based on inputs + current state.

Create / GATE Advanced (Q26–Q30)

Q26

[GATE Style] The minimum number of 2:1 MUXes required to implement a 4:1 MUX is:

GATECreate

✅ Answer: (B) 3 — Use 2 MUXes in the first level (each selects between 2 inputs using S0), then 1 MUX in the second level (selects between the two results using S1). Tree structure: 2 + 1 = 3 MUXes.

Q27

[GATE Style] A mod-10 counter requires a minimum of how many flip-flops?

GATECreate

✅ Answer: (B) 4 — Need to count 10 states (0–9). ⌈log₂(10)⌉ = ⌈3.32⌉ = 4 flip-flops. 3 FFs can only count 8 states (0–7). 4 FFs count up to 16 states; we reset at 10.

Q28

[GATE Style] To convert a JK flip-flop into a T flip-flop, the connections should be:

J = T, K = T'
J = T, K = T
J = T', K = T
J = 1, K = T

GATECreate

✅ Answer: (B) — Connect J = K = T. When T=0: J=K=0 → Hold (no change). When T=1: J=K=1 → Toggle. This matches T flip-flop behavior exactly.

Q29

[GATE Style] The output of a 3-bit ripple counter after 13 clock pulses (initial state = 000) is:

GATECreate

✅ Answer: (A) 101 — A 3-bit counter is Mod-8 (counts 0–7, then resets). 13 mod 8 = 5. Binary of 5 = 101.

Q30

[GATE Style] A 4:16 decoder can be constructed using:

Two 3:8 decoders and one 1:2 decoder
Four 2:4 decoders and one 2:4 decoder
Five 2:4 decoders
Both (A) and (C)

GATECreate

✅ Answer: (D) — Method 1: Use 2 MSBs to create 1:2 decoder (enable), feeding two 3:8 decoders (one for upper 8, one for lower 8). Method 2: Use 2 MSBs through a 2:4 decoder to enable four 2:4 decoders (each handling 4 outputs from the 2 LSBs). Both approaches work. 5 total 2:4 decoders = 1 (pre-decode) + 4 (output stage).

Section G

Short Answer Questions (8 Questions)

SA1: List and briefly explain the five functional units of a computer. [5 marks]

Answer:

1. Input Unit: Accepts data and instructions from external devices (keyboard, mouse, scanner). Converts human-readable data into binary for processing.

2. Memory Unit: Stores data and programs. Primary memory (RAM) holds active data; secondary memory (HDD/SSD) provides persistent storage. ROM stores firmware.

3. ALU (Arithmetic Logic Unit): Performs arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR, comparison).

4. Control Unit (CU): Directs the operation of all other units. Fetches instructions from memory, decodes them, and generates control signals to coordinate execution.

5. Output Unit: Presents processed results in human-readable form (monitor, printer, speaker). Converts binary data to visual/audio output.

These units communicate via three buses: Data Bus (data transfer), Address Bus (memory addressing), and Control Bus (control signals).

SA2: Differentiate between combinational and sequential circuits with two examples each. [5 marks]

Answer:

Parameter	Combinational	Sequential
Memory	No memory elements	Contains flip-flops (memory)
Feedback	No feedback path	Has feedback from output to input
Output depends on	Current inputs only	Current inputs + present state
Clock	Not required	Required (synchronous type)
Examples	Adder, MUX, Decoder, Encoder	Flip-flops, Counters, Registers

Indian analogy: Combinational = Vending machine (same input → same output, no history). Sequential = ATM (remembers card inserted, PIN entered — has states).

SA3: Design a Half Adder. Write its truth table, Boolean expressions, and draw the logic circuit. [5 marks]

Answer:

A Half Adder adds two single-bit inputs A and B, producing Sum (S) and Carry (C).

Truth Table: A=0,B=0→S=0,C=0 | A=0,B=1→S=1,C=0 | A=1,B=0→S=1,C=0 | A=1,B=1→S=0,C=1

Equations: S = A ⊕ B (XOR gate), C = A · B (AND gate)

Circuit: One XOR gate for Sum, one AND gate for Carry. Both gates take A and B as inputs. Total: 2 gates.

Limitation: Cannot handle carry input from a previous stage — hence "Half" adder. For multi-bit addition, we need Full Adders.

SA4: Explain the working of a JK flip-flop with its truth table and characteristic equation. [5 marks]

Answer:

The JK flip-flop is called the "universal" flip-flop because it eliminates the invalid state of the SR flip-flop.

Truth Table:

J=0, K=0 → Q(t+1) = Q(t) — No change (Hold)

J=0, K=1 → Q(t+1) = 0 — Reset

J=1, K=0 → Q(t+1) = 1 — Set

J=1, K=1 → Q(t+1) = Q'(t) — Toggle (key advantage over SR)

Characteristic Equation: Q(t+1) = J·Q'(t) + K'·Q(t)

Key Advantage: When J=K=1, the output toggles instead of entering an invalid state. This makes it ideal for counters (toggle mode) and convertible to D or T flip-flop configurations.

SA5: What is a Multiplexer? Explain 4:1 MUX with its truth table. [5 marks]

Answer:

A Multiplexer (MUX) is a combinational circuit that selects one of multiple input lines and directs it to a single output line. It acts as a "data selector."

4:1 MUX: Has 4 data inputs (I0–I3), 2 select lines (S1, S0), and 1 output (Y).

Truth Table: S1=0,S0=0→Y=I0 | S1=0,S0=1→Y=I1 | S1=1,S0=0→Y=I2 | S1=1,S0=1→Y=I3

Equation: Y = S1'·S0'·I0 + S1'·S0·I1 + S1·S0'·I2 + S1·S0·I3

Applications: Data routing, function implementation, communication systems. A 2ⁿ:1 MUX can implement any n-variable Boolean function, making it a universal logic element.

SA6: Explain the concept of Ripple Carry Adder. Why is it slow for large bit-widths? [5 marks]

Answer:

A Ripple Carry Adder (RCA) is formed by cascading n Full Adders to add two n-bit numbers. The carry-out of each FA becomes the carry-in of the next FA.

Why it's slow: The carry must "ripple" through all stages sequentially. FA(n) cannot compute its output until it receives carry from FA(n-1). Worst-case delay = 2n × gate_delay (2 gate levels per FA for carry).

Example: 32-bit RCA with 10 ns gate delay: Worst case = 2 × 32 × 10 = 640 ns → max frequency = 1.56 MHz. Modern CPUs need GHz speeds!

Solution: Carry Look-Ahead Adder (CLA) computes all carries in parallel using Generate and Propagate signals, achieving O(log n) delay instead of O(n).

SA7: What is a Decoder? How can a decoder be used to implement Boolean functions? [5 marks]

Answer:

A Decoder takes an n-bit input and activates exactly one of 2ⁿ output lines. Each output represents one minterm of the input variables.

2:4 Decoder Outputs: D0=A'B', D1=A'B, D2=AB', D3=AB — these are all 4 minterms of 2 variables.

Implementing Boolean functions: Since each decoder output is a minterm, any SOP function can be implemented by OR-ing the appropriate outputs.

Example: f(A,B) = Σm(1,3) = A'B + AB = D1 + D3. Connect D1 and D3 to an OR gate → output is f.

This makes decoders extremely versatile — an n:2ⁿ decoder + OR gates can implement ANY n-variable Boolean function.

SA8: Describe a 4-bit parallel register using D flip-flops. How does it load and store data? [5 marks]

Answer:

A 4-bit parallel register uses 4 D flip-flops with a common clock signal. Each FF stores one bit of the 4-bit data word.

Loading data: Place the 4-bit value on inputs D3, D2, D1, D0. On the rising edge of CLK, all four FFs simultaneously capture their respective D inputs: Q3←D3, Q2←D2, Q1←D1, Q0←D0.

Storing data: Between clock edges, the outputs Q3–Q0 hold the stored value. The data persists until the next clock edge loads new values.

Applications: CPU general-purpose registers (store operands), instruction register (holds current instruction), buffer registers in data transfer, shift registers for serial-to-parallel conversion.

Example: Intel x86 has 32-bit registers (EAX, EBX, etc.) — each is essentially 32 D flip-flops with a common clock.

Section H

Long Answer Questions (3 Questions)

LA1: Design a 4-bit Ripple Carry Adder. Explain its working with a complete example, draw the circuit diagram, and discuss its limitations. Suggest an improvement. [15 marks]

Model Answer:

Introduction: A 4-bit Ripple Carry Adder (RCA) adds two 4-bit binary numbers A = A3A2A1A0 and B = B3B2B1B0 with an optional carry-in C0, producing a 4-bit sum S = S3S2S1S0 and a carry-out C4.

Building Block — Full Adder:

Each FA has inputs (Ai, Bi, Ci) and outputs (Si, Ci+1).

Sum: Si = Ai ⊕ Bi ⊕ Ci | Carry: Ci+1 = Ai·Bi + Ci·(Ai ⊕ Bi)

Circuit: Four FAs cascaded — Cout of FA(i) connects to Cin of FA(i+1). C0 is typically 0 for addition.

Worked Example: Add A = 0111 (7) and B = 0101 (5):

  FA0: 1+1+0 = 10 → S0=0, C1=1
  FA1: 1+0+1 = 10 → S1=0, C2=1  
  FA2: 1+1+1 = 11 → S2=1, C3=1
  FA3: 0+0+1 = 01 → S3=1, C4=0
  Result: 1100₂ = 12₁₀ ✓ (7+5=12)

Limitations:

Propagation Delay: Carry ripples through all n stages. Worst-case delay = 2n × t_gate. For 64-bit: 128 × t_gate — unacceptable for GHz processors.
Speed inversely proportional to bit-width: Longer adders are proportionally slower.
Not suitable for high-speed applications: Modern CPUs require single-cycle addition.

Improvement — Carry Look-Ahead Adder (CLA):

Define: Generate Gi = Ai·Bi (carry generated regardless of Cin), Propagate Pi = Ai ⊕ Bi (carry propagated from Cin).

C1 = G0 + P0·C0, C2 = G1 + P1·G0 + P1·P0·C0, etc.

All carries computed in parallel → O(log n) delay instead of O(n). Used in all modern processors.

LA2: Compare all four types of flip-flops (SR, D, JK, T). For each, provide the truth table, characteristic equation, excitation table, and one practical application. Explain how to convert a JK flip-flop into D and T flip-flops. [15 marks]

Model Answer:

1. SR Flip-Flop: Truth Table: 00→Hold, 01→Reset(0), 10→Set(1), 11→Invalid. Char. Eq: Q(t+1) = S + R'Q, Constraint: SR=0. Excitation: 0→0: S=0,R=X | 0→1: S=1,R=0 | 1→0: S=0,R=1 | 1→1: S=X,R=0. Application: Simple latch circuits, debouncing switches.

2. D Flip-Flop: Truth Table: D=0→Q=0, D=1→Q=1. Char. Eq: Q(t+1) = D. Excitation: 0→0: D=0 | 0→1: D=1 | 1→0: D=0 | 1→1: D=1. Application: Data registers, pipeline stages in processors.

3. JK Flip-Flop: Truth Table: 00→Hold, 01→Reset, 10→Set, 11→Toggle. Char. Eq: Q(t+1) = JQ' + K'Q. Excitation: 0→0: J=0,K=X | 0→1: J=1,K=X | 1→0: J=X,K=1 | 1→1: J=X,K=0. Application: Counters, universal flip-flop, state machines.

4. T Flip-Flop: Truth Table: T=0→Hold, T=1→Toggle. Char. Eq: Q(t+1) = T⊕Q. Excitation: 0→0: T=0 | 0→1: T=1 | 1→0: T=1 | 1→1: T=0. Application: Binary counters, frequency dividers.

Conversions:

JK → D: We need Q(t+1) = D. Set J = D, K = D'. Proof: JQ' + K'Q = DQ' + D'·'Q = DQ' + DQ = D(Q'+Q) = D ✓

JK → T: We need Q(t+1) = T⊕Q. Set J = K = T. Proof: TQ' + T'Q = T⊕Q ✓ (by definition of XOR).

LA3: Design a 3-bit synchronous up-counter using JK flip-flops. Provide the state table, excitation table, K-map simplification for each flip-flop input, circuit diagram, and timing diagram. [15 marks]

Model Answer:

State Table:

  Present State → Next State
  Q2 Q1 Q0    → Q2+ Q1+ Q0+
   0  0  0    →  0   0   1
   0  0  1    →  0   1   0
   0  1  0    →  0   1   1
   0  1  1    →  1   0   0
   1  0  0    →  1   0   1
   1  0  1    →  1   1   0
   1  1  0    →  1   1   1
   1  1  1    →  0   0   0

Excitation Table (JK FF: 0→0: J=0,K=X | 0→1: J=1,K=X | 1→0: J=X,K=1 | 1→1: J=X,K=0):

  Q2 Q1 Q0 | J2 K2 | J1 K1 | J0 K0
   0  0  0 |  0  X |  0  X |  1  X
   0  0  1 |  0  X |  1  X |  X  1
   0  1  0 |  0  X |  X  0 |  1  X
   0  1  1 |  1  X |  X  1 |  X  1
   1  0  0 |  X  0 |  0  X |  1  X
   1  0  1 |  X  0 |  1  X |  X  1
   1  1  0 |  X  0 |  X  0 |  1  X
   1  1  1 |  X  1 |  X  1 |  X  1

K-Map Simplification:

J0 = K0 = 1 (always toggle — all J0 entries are 1 or X, all K0 entries are 1 or X)

J1 = K1 = Q0 (J1 is 1 when Q0=1, K1 is 1 when Q0=1)

J2 = K2 = Q1·Q0 (J2 is 1 only when Q1=1 AND Q0=1)

Circuit: Three JK FFs with common clock. FF0: J0=K0=1. FF1: J1=K1=Q0. FF2: J2=K2=Q0·Q1 (AND gate). This is a synchronous counter — all FFs triggered by the same clock edge simultaneously.

Timing Diagram: Q0 toggles every clock edge. Q1 toggles when Q0=1 at clock edge. Q2 toggles when Q0=Q1=1 at clock edge. Count sequence: 000→001→010→011→100→101→110→111→000.

Section I

Industry Spotlight — A Day in the Life

👩‍💻 Priya Sharma, 28 — VLSI Design Engineer at Intel India, Bangalore

Background: B.Tech ECE from NIT Trichy. Loved digital electronics in 2nd year. Did a summer internship at Texas Instruments. Got placed at Intel through campus recruitment at ₹12 LPA (2019). Now at ₹22 LPA after 5 years.

A Typical Day:

9:00 AM — Standup call with the Xeon server chip team. Review RTL (Register Transfer Level) code changes from yesterday. Discuss a timing violation in the integer ALU path.

10:00 AM — Write Verilog HDL code for a 64-bit Carry Look-Ahead Adder module. Every gate, every flip-flop she designs uses the exact concepts from this chapter — at industrial scale.

12:00 PM — Run synthesis and timing analysis using Synopsys Design Compiler. The tool reports that her adder meets the 4 GHz target clock — carry delay is under 250 ps.

2:00 PM — Review a colleague's counter design for the branch predictor unit. Check state transitions, verify excitation table against the specification.

4:00 PM — Debug a simulation failure: a JK flip-flop in the instruction queue has an unexpected toggle. Root cause — a race condition in asynchronous reset logic.

5:30 PM — Knowledge-sharing session: presents "Adder Architectures — From Ripple to Kogge-Stone" to junior engineers. The slides start with the same Half Adder truth table you learned today.

Detail	Info
Tools Used Daily	Verilog/VHDL, Synopsys Design Compiler, Cadence Virtuoso, ModelSim, Python scripting
Entry Salary (2024)	₹10–15 LPA (Intel, TI, Qualcomm, Samsung Semiconductor)
Mid-Level (3–5 yrs)	₹18–30 LPA
Senior (8+ yrs)	₹35–60 LPA
Companies Hiring	Intel India (Bangalore), Qualcomm (Hyderabad), Texas Instruments (Bangalore), Samsung Semiconductor (Noida), AMD, Broadcom, MediaTek, Synopsys, Cadence
Key Exam Paths	GATE ECE/CS (for M.Tech → VLSI specialization at IITs), ISRO Scientist, DRDO SET

The India Semiconductor Mission (ISM) has earmarked ₹76,000 crore for chip manufacturing. Companies like Tata Electronics (Dholera fab), CG Power (OSAT), and Micron (Gujarat) are hiring thousands of VLSI engineers. The skills you're learning in this chapter are directly applicable — digital design is the foundation of every chip.

Section J

Earn With It — Tutoring & Freelance Roadmap

💰 Your Earning Path After This Unit

Primary Earning Avenue: Digital Electronics tutoring for engineering students and GATE aspirants.

Why this works: COA and Digital Electronics are compulsory subjects across all engineering branches (CSE, ECE, EEE, IT). Thousands of students struggle with flip-flops, K-maps, and counter design every semester.

Earning Avenue	Description	Rate
Peer Tutoring	Help batchmates with Digital Electronics assignments, lab prep, and exam revision	₹400–600/hr
GATE Coaching	Teach COA + Digital Logic to GATE aspirants. Focus on previous year questions.	₹600–1000/hr
Online Tutoring	Platforms: Chegg, Doubtnut, Vedantu (for competitive exams). Solve doubt questions.	₹300–800/hr
YouTube / Notes	Create animated flip-flop tutorials, counter design walkthroughs. Monetize with ads.	₹5,000–15,000/month (at 10K+ views)
Lab Assignment Help	Help juniors with Verilog/VHDL lab programs (ethically — teach, don't copy)	₹500–1000/assignment
Internshala Projects	Digital circuit simulation projects using Logisim or Proteus	₹2,000–5,000/project

⏱️ Time to First Earning: 1–2 weeks (start by tutoring your own classmates who are struggling with flip-flops)

The GATE coaching market in India is worth ₹4,000+ crore. Even micro-tutoring (solving 10 doubts/day on Chegg at ₹80/doubt) = ₹800/day = ₹24,000/month. Combined with peer tutoring, a student strong in digital electronics can easily earn ₹10,000–25,000/month while still in college.

Portfolio builder: Create a "Digital Circuit Simulator" using Python (you started in Tier 3 lab). Upload to GitHub. This demonstrates both programming AND digital design skills — impressive for VLSI internship applications at Intel, TI, or Qualcomm India.

Section K

Chapter Summary & Unit Map

🗺️ Unit 1 Summary — Digital Systems at a Glance

Core Architecture: Every computer has 5 units — Input, Output, Memory, ALU, and Control Unit — connected by Data, Address, and Control buses.

Combinational Circuits (no memory, no clock):

Half Adder: S = A⊕B, C = A·B (adds 2 bits)
Full Adder: S = A⊕B⊕Cin, Cout = AB + Cin(A⊕B) (adds 3 bits)
4:1 MUX: Selects 1 of 4 inputs using 2 select lines. Universal logic element.
2:4 Decoder: Activates 1 of 4 outputs. Each output = one minterm.
Encoder: Reverse of decoder. Priority encoder handles multiple active inputs.
Ripple Carry Adder: n Full Adders cascaded. Delay = O(n). Slow for large n.

Sequential Circuits (has memory, clock-driven):

SR FF: Set/Reset. Q(t+1) = S + R'Q. Invalid when S=R=1.
D FF: Data/Delay. Q(t+1) = D. Used in registers.
JK FF: Universal. Q(t+1) = JQ' + K'Q. Toggles when J=K=1.
T FF: Toggle. Q(t+1) = T⊕Q. Used in counters.
Register: Group of D FFs with common clock. Stores n-bit data.
Counter: Sequential counter using T/JK FFs. Mod-2ⁿ for n-bit.

Key Formulas for GATE:

FFs needed for Mod-N counter: ⌈log₂N⌉
RCA delay: 2n × gate_delay
2ⁿ:1 MUX select lines: n
n:2ⁿ decoder outputs: 2ⁿ minterms

  ╔══════════════════════════════════════════════════════════════╗
  ║                  UNIT 1 — CONCEPT MAP                       ║
  ╠══════════════════════════════════════════════════════════════╣
  ║                                                              ║
  ║  ┌──────────────────┐      ┌──────────────────────┐         ║
  ║  │   DIGITAL        │      │   5-UNIT COMPUTER     │         ║
  ║  │   SYSTEMS        │─────►│   MODEL               │         ║
  ║  └────────┬─────────┘      │   (Input, Output,     │         ║
  ║           │                │    Memory, ALU, CU)    │         ║
  ║           │                └──────────────────────┘         ║
  ║           │                                                  ║
  ║     ┌─────┴──────┐                                          ║
  ║     │            │                                          ║
  ║     ▼            ▼                                          ║
  ║  ┌──────┐    ┌──────┐                                       ║
  ║  │COMBI-│    │SEQU- │                                       ║
  ║  │NATION│    │ENTIAL│                                       ║
  ║  │AL    │    │      │                                       ║
  ║  └──┬───┘    └──┬───┘                                       ║
  ║     │           │                                           ║
  ║  ┌──┴────────┐  ├── SR Flip-Flop                            ║
  ║  ├─ Adders   │  ├── D Flip-Flop                             ║
  ║  │  (HA, FA) │  ├── JK Flip-Flop                            ║
  ║  ├─ MUX      │  ├── T Flip-Flop                             ║
  ║  ├─ Decoder  │  ├── Registers                               ║
  ║  ├─ Encoder  │  └── Counters                                ║
  ║  └─ RCA/CLA  │                                              ║
  ║              ▼                                              ║
  ║     ┌─────────────────────────────┐                         ║
  ║     │  APPLICATIONS               │                         ║
  ║     │  ISRO PSLV, Intel CPUs,     │                         ║
  ║     │  Qualcomm SoCs, ARM cores   │                         ║
  ║     └─────────────────────────────┘                         ║
  ╚══════════════════════════════════════════════════════════════╝

Section L

Earning Checkpoint — Self-Assessment

Use this table to track your mastery and earning readiness for each skill learned in this unit:

Skill / Topic	Tool / Method	Portfolio Piece	Earning Ready?
5-Unit Computer Model	Conceptual	—	✅ Yes — can explain in interviews/tutoring
Truth Tables & Gate Design	Pen & Paper, Python	Truth Table Generator (Python)	✅ Yes — tutor juniors ₹400–600/hr
Combinational Circuits	Adders, MUX, Decoder	Full Adder trace + 4-bit RCA design	✅ Yes — GATE coaching ₹600–1000/hr
Sequential Circuits	Flip-flops, Counters	3-bit Counter Design	✅ Yes — most-asked topic in exams
GATE Problem Solving	Previous Year Papers	Solved GATE problems with explanations	✅ Yes — online doubt-solving ₹80/doubt
Python Circuit Simulator	Python (itertools)	GitHub project — Truth Table Generator	✅ Yes — impressive for VLSI internships
Verilog/VHDL (Next Step)	HDL coding	—	⬜ Not yet — covered in Unit 3

Minimum Viable Earning Setup after this unit: Master flip-flop truth tables + counter design + GATE PYQs → start tutoring classmates and GATE aspirants → earn ₹10,000–25,000/month while still in college. Add Python circuit simulator to GitHub → stand out in VLSI company interviews.

✅ Unit 1 complete. Ready for Unit 2: Data Representation & Number Systems!

[QR: Link to EduArtha video tutorial — Basics of Digital Systems]

A	B	Cin	P=A⊕B	G=A·B	T=P·Cin	Sum=P⊕Cin	Cout=G+T
0	0	0	0	0	0	0	0
0	0	1	0	0	0	1	0
0	1	0	1	0	0	1	0
0	1	1	1	0	1	0	1
1	0	0	1	0	0	1	0
1	0	1	1	0	1	0	1
1	1	0	0	1	0	0	1
1	1	1	0	1	0	1	1

A	B	Cin	P=A⊕B	G=A·B	T=P·Cin	Sum=P⊕Cin	Cout=G+T
0	0	0	0	0	0	0	0
0	0	1	0	0	0	1	0
0	1	0	1	0	0	1	0
0	1	1	1	0	1	0	1
1	0	0	1	0	0	1	0
1	0	1	1	0	1	0	1
1	1	0	0	1	0	0	1
1	1	1	0	1	0	1	1

A	B	Cin	P=A⊕B	G=A·B	T=P·Cin	Sum=P⊕Cin	Cout=G+T
0	0	0	0	0	0	0	0
0	0	1	0	0	0	1	0
0	1	0	1	0	0	1	0
0	1	1	1	0	1	0	1
1	0	0	1	0	0	1	0
1	0	1	1	0	1	0	1
1	1	0	0	1	0	0	1
1	1	1	0	1	0	1	1