Computer Organization & Architecture
Unit 6: Memory Unit
From registers to hard drives — master the memory hierarchy, cache mapping techniques, virtual memory, and solve GATE-level numericals with confidence.
⏱️ 8 hrs theory + 5 hrs lab | 🎯 GATE ~4 marks | 🖥️ Snapdragon Cache
💼 Jobs this unlocks: VLSI Design Engineer (₹6–12 LPA) | Embedded Systems Developer (₹5–10 LPA) | SoC Verification Engineer (₹8–15 LPA)
Opening Hook — Why Does Your Laptop Slow Down with 100 Tabs?
🖥️ The Mystery of the 100-Tab Slowdown
You've done it. We all have. You open Chrome, start with 5 tabs, then 20, then 50… and by the time you hit 100 tabs, your laptop turns into a space heater that can barely scroll. Your fancy 16 GB RAM machine is now slower than a ₹5,000 phone. Why?
The answer lies in the memory hierarchy. Your CPU doesn't just grab data from RAM. It first checks its tiny ultra-fast L1 cache (32 KB, ~1 ns). Miss? It checks the L2 cache (256 KB, ~5 ns). Still miss? L3 cache (8 MB, ~20 ns). All misses? It finally goes to RAM (16 GB, ~100 ns). But with 100 tabs, even RAM fills up, and the OS starts using your SSD as virtual memory — that's 1000× slower than RAM. That's the slowdown.
Qualcomm's Snapdragon 8 Gen 3 chip (inside your Samsung Galaxy S24) has a 12 MB L3 cache designed by Indian engineers in Hyderabad. Apple's M3 has a 36 MB L2. Every nanosecond saved in cache design translates to billions of dollars in market advantage. This chapter teaches you exactly how that works.
Learning Outcomes — Bloom's Taxonomy Mapped
| Bloom's Level | Learning Outcome |
|---|---|
| 🔵 Remember | List the levels of the memory hierarchy with access times, sizes, and cost per bit |
| 🔵 Remember | Define cache memory, hit ratio, miss penalty, TLB, and page fault |
| 🟢 Understand | Explain how direct mapping, fully associative, and set-associative mapping work with tag/line/word fields |
| 🟢 Understand | Describe virtual memory organisation including page tables, TLB, and demand paging |
| 🟡 Apply | Compute tag, line, and word bits for a given cache configuration and calculate AMAT |
| 🟡 Apply | Trace a reference string through cache using FIFO replacement and calculate hit rate |
| 🟠 Analyze | Compare write-through vs write-back policies and analyse their performance trade-offs |
| 🟠 Analyze | Analyse why set-associative mapping is preferred over direct and fully associative in modern CPUs |
| 🔴 Evaluate | Evaluate the cache design trade-offs in Snapdragon vs Apple Silicon processors |
| 🔴 Evaluate | Assess the impact of page size on TLB miss rate and internal fragmentation |
| 🟣 Create | Design a 2-level cache hierarchy for a given workload with AMAT constraints |
| 🟣 Create | Simulate a cache replacement algorithm for a given reference string and propose optimisations |