Computer Organization & Architecture

Unit 4: Central Processing Unit

From register files to interrupt handling — master CPU internals, instruction formats, addressing modes, and the RISC vs CISC battle that shapes every processor in your pocket.

⏱️ 7 hrs theory + 5 hrs lab | 🎯 GATE ~4 marks | 🖥️ ARM vs Intel

💼 Jobs this unlocks: VLSI Design Engineer (₹6–12 LPA) | Embedded Systems Engineer (₹5–10 LPA) | CPU Verification Engineer (₹8–18 LPA)

Section A

Opening Hook — Apple M4 vs Snapdragon X Elite: The CPU War

🔥 The RISC vs CISC Battle That Changed Computing Forever

In 2024, Apple unveiled the M4 chip — an ARM-based RISC processor that obliterates Intel's Core Ultra in performance-per-watt. A MacBook Pro with M4 delivers 38 trillion operations per second while sipping battery like a phone. Meanwhile, Qualcomm's Snapdragon X Elite brought ARM to Windows laptops, threatening Intel's 40-year x86 CISC monopoly on PCs.

Here's the twist: both M4 and Snapdragon X Elite are RISC processors — they use a reduced instruction set with fixed-length instructions. Intel's Core Ultra and AMD's Ryzen are CISC processors — complex instruction sets with variable-length instructions. For decades, everyone thought CISC won the PC war. Now RISC is eating CISC's lunch.

Behind every chip is a CPU architecture built from register files, ALUs, instruction decoders, and interrupt controllers — exactly what this chapter teaches you. Understand this chapter, and you'll understand why Apple's stock is worth $3 trillion.

🍎 Apple📱 Qualcomm💻 Intel🔴 AMD🇬🇧 ARM Holdings🇰🇷 Samsung

India is designing its own CPU! IIT Madras developed the SHAKTI processor — India's first indigenous RISC-V CPU. RISC-V is an open-source instruction set architecture (no licensing fees, unlike ARM). India's MeitY is investing ₹76,000 crore in semiconductor manufacturing under the India Semiconductor Mission. By 2030, Indian engineers may be designing CPUs rivalling Qualcomm and MediaTek.

Section B

Learning Outcomes — Bloom's Taxonomy Mapped

Bloom's Level	Learning Outcome
🔵 Remember	List all 8 addressing modes and define RISC vs CISC architectures
🔵 Remember	Identify components of General Register Organization: register file, MUX, ALU, output bus
🔵 Understand	Explain stack organization with PUSH/POP operations and Stack Pointer movement
🔵 Understand	Describe how 3-address, 2-address, 1-address, and 0-address instruction formats encode operations
🟢 Apply	Evaluate X=(A+B)*(C+D) using all four instruction formats with complete instruction sequences
🟢 Apply	Trace flag changes (CF, ZF, SF, OF) in the PSW after arithmetic operations like ADD 0x7FFF+0x0001
🟠 Analyze	Compare RISC vs CISC across 12+ parameters with ARM vs x86 real-world examples
🟠 Analyze	Determine effective addresses for all 8 addressing modes given memory contents and register values
🔴 Evaluate	Justify when to use stack organization vs register organization for different application scenarios
🔴 Evaluate	Assess interrupt priority handling schemes (daisy-chain vs parallel) for real-time embedded systems
🟣 Create	Design a simple instruction set with 16 instructions supporting at least 4 addressing modes
🟣 Create	Architect a CPU datapath for a given 3-address instruction format with control signals