Computer Organization & Architecture
Unit 3: Computer Organization
From instruction codes to interrupt handling — master Mano's Basic Computer architecture, the common bus system, and the complete instruction cycle used in every modern processor.
⏱️ 7 hrs theory + 5 hrs lab | 🎯 GATE ~4 marks | 🖥️ Mano's Basic Computer
💼 Jobs this unlocks: Hardware Design Engineer (₹6–10 LPA) | VLSI Engineer (₹8–15 LPA) | Embedded Systems (₹5–9 LPA)
Opening Hook — The Brain Inside Your Phone
🏢 Qualcomm Snapdragon 8 Gen 3 — The ₹80,000-Crore Bus Architecture in Your Pocket
When you unlock your OnePlus 12 or Samsung Galaxy S24 Ultra, a marvel of computer organization springs to life. The Qualcomm Snapdragon 8 Gen 3 chip inside contains over 20 billion transistors on a die smaller than your fingernail. But raw transistors are useless without organisation — how data moves between the CPU cores, memory, GPU, and I/O peripherals.
At the heart of this chip lies a bus architecture — a set of shared communication pathways that connect the Kryo CPU cores, the Adreno 750 GPU, the Hexagon DSP, and LPDDR5X memory. Every instruction you trigger — opening Instagram, running a BGMI match, scanning a UPI QR code — travels through this bus system at speeds exceeding 4 GHz. The bus must arbitrate: Who gets to talk? In what order? How does the CPU fetch the next instruction while the GPU renders a frame?
This chapter teaches you exactly how a computer is organised internally — using Mano's Basic Computer as the foundational model. Every concept here — registers, buses, instruction cycles, interrupts — maps directly to what happens inside that Snapdragon chip. Understanding this is the difference between a coder and a computer engineer.
Learning Outcomes — Bloom's Taxonomy Mapped (12 Outcomes)
| Bloom's Level | Learning Outcome |
|---|---|
| 🔵 Remember | LO1: List all 8 registers of Mano's Basic Computer with their bit-widths and functions |
| 🔵 Remember | LO2: State the 16-bit instruction format: I(1) + Opcode(3) + Address(12) and recall all 7 memory-reference opcodes |
| 🟢 Understand | LO3: Explain how the common bus system uses MUX selection lines S₂S₁S₀ to route data between registers |
| 🟢 Understand | LO4: Describe the Fetch-Decode-Execute cycle with timing signals T₀, T₁, T₂ and their micro-operations |
| 🟡 Apply | LO5: Trace the complete execution of any memory-reference instruction (AND, ADD, LDA, STA, BUN, BSA, ISZ) through all timing states |
| 🟡 Apply | LO6: Write RTL (Register Transfer Language) micro-operations for each instruction and timing signal |
| 🟠 Analyze | LO7: Compare hardwired vs microprogrammed control units — speed, flexibility, complexity, and use cases |
| 🟠 Analyze | LO8: Analyze the interrupt cycle and determine how IEN, FGI, FGO flags interact to handle I/O |
| 🔴 Evaluate | LO9: Evaluate design trade-offs in bus width, register count, and instruction format for a basic CPU |
| 🔴 Evaluate | LO10: Justify why Mano's 25-instruction architecture is sufficient to demonstrate Turing-completeness |
| 🟣 Create | LO11: Design a simple CPU simulator that implements the fetch-decode-execute cycle for Mano's instructions |
| 🟣 Create | LO12: Construct timing diagrams and control signal tables for a new custom instruction added to Mano's ISA |